8 using the 24-bit audio codec, Using the 24-bit audio codec, Figure 5.14. audio codec schematic – SIGMA DE2-70 User Manual

Page 51: Table 5.12. audio codec pin assignments, De2-70 user manual

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DE2-70 User Manual

48


5.8 Using the 24-bit Audio CODEC

The DE2-70 board provides high-quality 24-bit audio via the Wolfson WM8731 audio CODEC

(enCOder/DECoder). This chip supports microphone-in, line-in, and line-out ports, with a sample

rate adjustable from 8 kHz to 96 kHz. The WM8731 is controlled by a serial I2C bus interface,

which is connected to pins on the Cyclone II FPGA. A schematic diagram of the audio circuitry is

shown in Figure 5.14, and the FPGA pin assignments are listed in Table 5.12. Detailed information

for using the WM8731 codec is available in its datasheet, which can be found on the manufacturer's

web site, or in the Datasheet/Audio CODEC folder on the DE2-70 System CD-ROM.

I2C_SDAT

AUD_BCLK

AUD_DACLRCK

AUD_ADCLRCK

AUD_DACDAT

I2C_SCLK

AUD_XCK

AUD_ADCD AT

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

A_VCC33

A_VCC33

A_VCC33

VCC33

VCC33

I2C ADDRESS READ IS 0x34

I2C ADDRESS WRITE IS 0x35

LINE IN

MIC IN

LINE OUT

R104

680

R104

680

C38

1u

C38

1u

C39

1u

C39

1u

R103

330

R103

330

R106

47K

R106

47K

C42

1n

C42

1n

C44

100u

C44

100u

J10

PHONE JACK P

J10

PHONE JACK P

L

1

R

2

G

N

D

3

N

C

R

4

N

C

L

5

C40

1u

C40

1u

J11

PHONE JACK B

J11

PHONE JACK B

L

1

R

2

G

N

D

3

N

C

R

4

N

C

L

5

R107

47K

R107

47K

C43

100u

C43

100u

R105

47K

R105

47K

R102

4.7K

R102

4.7K

R108

2K

R108

2K

R101

4.7K

R101

4.7K

R109

2K

R109

2K

U13

WM8731

U13

WM8731

BCLK

7

H

P

V

D

D

12

XTO

2

DCVDD

3

MBIAS

21

M

IC

IN

22

R

LI

N

E

IN

23

LLI

N

E

IN

24

M

O

D

E

25

C

S

B

26

S

D

IN

27

S

C

LK

28

ROUT

17

AVDD

18

AGND

19

VMID

20

LOUT

16

HPGND

15

R

H

P

O

U

T

14

LH

P

O

U

T

13

XTI/MCLK

1

DGND

4

A

D

C

LR

C

K

11

A

D

C

D

A

T

10

DBVDD

5

CLKOUT

6

D

A

C

D

A

T

8

D

A

C

LR

C

K

9

E

X

P

O

S

E

D

29

R100

4.7K

R100

4.7K

J12

PHONE JACK G

J12

PHONE JACK G

L

1

R

2

G

N

D

3

N

C

R

4

N

C

L

5

C41

10u

C41

10u

R99

4.7K

R99

4.7K

Figure 5.14. Audio CODEC schematic.

Signal Name

FPGA Pin No.

Description

AUD_ADCLRCK

PIN_F19

Audio CODEC ADC LR Clock

AUD_ADCDAT

PIN_E19

Audio CODEC ADC Data

AUD_DACLRCK

PIN_G18

Audio CODEC DAC LR Clock

AUD_DACDAT

PIN_F18

Audio CODEC DAC Data

AUD_XCK

PIN_D17

Audio CODEC Chip Clock

AUD_BCLK

PIN_E17

Audio CODEC Bit-Stream Clock

I2C_SCLK PIN_J18

I2C

Data

I2C_SDAT PIN_H18

I2C

Clock

Table 5.12. Audio CODEC pin assignments.

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