SMSC LAN9500 - Manual (Page 42)

Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
Revision 1.7 (10-02-08) 42 SMSC LAN9500/LAN9500i
DATASHEET
Chapter 6 Revision History
Table 6.1 Customer Revision History
REVISION LEVEL
AND DATE SECTION/FIGURE/ENTRY CORRECTION
Rev. 1.6
(09-09-08)
All Fixed various typos
Table 3.4, “Dump of EEPROM
Memory,” on page 23 Fixed typos in example
Table 3.5, “EEPROM Example -
256 Byte EEPROM,” on page 24 Fixed typos in example
Table 2.4, “Miscellaneous Pins,” on
page 14 Added note to GPIO8, GPIO9, and GPIO10 stating
“By default this pin is configured as a GPIO”
Rev. 1.5
(08-27-08)
All Fixed various typos
Table 4.6, “I/O Buffer
Characteristics,” on page 31 Input leakage and input capacitance values added
for IS and IS_5V buffer types.
Table 2.1, “MII Interface Pins,” on
page 10 Added note to EEP_SIZE pin definition: “A 3-wire
style 1K/2K/4K EEPROM that is organized for 128
x 8-bit or 256/512 x 8-bit operation must be used.”
Chapter 3, "EEPROM Controller
(EPC)," on page 20 EEPROM Controller section added.
Rev. 1.3
(06-30-08)
Section 4.3, "Power
Consumption," on page 29 Added SUSPEND0 and SUSPEND1 power
consumption tables. Reformatted all power
consumption tables and added typical values,
except for customer evaluation board, for which
maximum value was specified.
Rev. 1.2
(06-18-08)
Chapter 2, "Pin Description and
Configuration," on page 9 Added IS buffer type to following pins when
operating in Internal PHY Mode: RXER, TXEN,
RXDV, RXCLK, CRS, COL, MDIO, MDC, TXD3,
TXD2, TXD1, TXD0, TXCLK.
Chapter 2, "Pin Description and
Configuration," on page 9 Added PD buffer type to following pins when
operating in Internal PHY Mode: TXEN, RXDV,
COL, MDIO, MDC, TXD3, TXD2, TXD1, TXD0,
TXCLK.
Chapter 2, "Pin Description and
Configuration," on page 9 Changed buffer type from PU to PD for following
pins: TXD2 (Internal PHY Mode), TXD1 (Internal
PHY Mode), TXD0 (Internal PHY Mode).
Chapter 2, "Pin Description and
Configuration," on page 9 Changed buffer type from PD to PU for following
pins: TXD3 (External PHY Mode).
Rev. 1.2
(06-16-08)
Table 4.14, “LAN9500/LAN9500i
Crystal Specifications,” on page 39 Changed ESR value from 30 ohms max to 50
ohms max.
Rev. 1.2
(06-10-08)
Table 2.9, “56-QFN Package Pin
Assignments,” on page 18 Changed pin 33 from “NC” to “TEST3”
Table 2.8, “No-Connect Pins,” on
page 17 Reduced pin count to one. Removed hidden
TESTMODE entry from the table.