Document Outline

• Chapter 1 Introduction
  • 1.1 Block Diagram
    • Figure 1.1 LAN9500/LAN9500i System Diagram
    • 1.1.1 Overview
    • 1.1.2 USB
    • 1.1.3 FIFO Controller
    • 1.1.4 Ethernet
    • 1.1.5 Power Management
    • 1.1.6 EEPROM Controller
    • 1.1.7 General Purpose I/O
• Chapter 2 Pin Description and Configuration
  • Figure 2.1 LAN9500/LAN9500i 56-QFN Pin Assignments (TOP VIEW)
  • Table 2.1 MII Interface Pins
  • Table 2.2 EEPROM Pins
  • Table 2.3 JTAG Pins
  • Table 2.4 Miscellaneous Pins
  • Table 2.5 USB Pins
  • Table 2.6 Ethernet PHY Pins
  • Table 2.7 I/O Power Pins, Core Power Pins, and Ground Pad
  • Table 2.8 No-Connect Pins
  • Table 2.9 56-QFN Package Pin Assignments
  • 2.1 Buffer Types
    • Table 2.10 Buffer Types
• Chapter 3 EEPROM Controller (EPC)
  • 3.1 EEPROM Format
    • Table 3.1 EEPROM Format
    • Table 3.2 Configuration Flags Description
  • 3.2 EEPROM Defaults
    • Table 3.3 EEPROM Defaults
  • 3.3 EEPROM Auto-Load
  • 3.4 An Example of EEPROM Format Interpretation
    • Table 3.4 Dump of EEPROM Memory
    • Table 3.5 EEPROM Example - 256 Byte EEPROM
• Chapter 4 Operational Characteristics
  • 4.1 Absolute Maximum Ratings*
  • 4.2 Operating Conditions**
  • 4.3 Power Consumption
    • 4.3.1 SUSPEND0
      • Table 4.1 SUSPEND0 - Supply and Current @3.3V
    • 4.3.2 SUSPEND1
      • Table 4.2 SUSPEND1 - Supply and Current @3.3V
    • 4.3.3 SUSPEND2
      • Table 4.3 SUSPEND2 - Supply and Current @3.3V
    • 4.3.4 Operational Power Consumption
      • Table 4.4 Operational Power Consumption - Supply and Current @3.3V
    • 4.3.5 Customer Evaluation Board Operational Power Consumption
      • Table 4.5 Customer Evaluation Board Operational Power Consumption - Supply and Current @3.3V
  • 4.4 DC Specifications
    • Table 4.6 I/O Buffer Characteristics
    • Table 4.7 100BASE-TX Transceiver Characteristics
    • Table 4.8 10BASE-T Transceiver Characteristics
  • 4.5 AC Specifications
    • 4.5.1 Equivalent Test Load
      • Figure 4.1 Output Equivalent Test Load
    • 4.5.2 Power-On Configuration Strap Valid Timing
      • Figure 4.2 Power-On Configuration Strap Valid Timing
      • Table 4.9 Power-On Configuration Strap Valid Timing
    • 4.5.3 Reset and Configuration Strap Timing
      • Figure 4.3 nRESET Reset Pin Timing
      • Table 4.10 nRESET Reset Pin Timing Values
    • 4.5.4 EEPROM Timing
      • Figure 4.4 EEPROM Timing
      • Table 4.11 EEPROM Timing Values
    • 4.5.5 Turbo MII Interface Timing
      • Figure 4.1 Turbo MII Output Timing
      • Table 4.12 Turbo MII Output Timing Values
      • Figure 4.2 Turbo MII Input Timing
      • Table 4.13 Turbo MII Interface Timing Values
  • 4.6 Clock Circuit
    • Table 4.14 LAN9500/LAN9500i Crystal Specifications
• Chapter 5 Package Outline
  • Figure 5.1 LAN9500/LAN9500i 56-QFN Package
  • Table 5.1 LAN9500/LAN9500i 56-QFN Dimensions
  • Figure 5.2 LAN9500/LAN9500i 56-QFN Recommended PCB Land Pattern
• Chapter 6 Revision History
  • Table 6.1 Customer Revision History