PMC-Sierra PM5354 - Manual

PM5354
Multi-rate SATURN User Network Interface for 2x622 and 4x155
S/UNI MULTI 2x12
PMC-2021540 (R3) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE © Copyright PMC-Sierra, Inc. 2003
Released
FEATURES
• Single chip ATM and POS User
Network Interface that supports up to
2x622.08 Mbit/s, 4x155.52 Mbit/s,
1x622.08 + 3x155.52 Mbit/s, or
2x622.08 Mbit/s + 2x155.52 Mbit/s.
• Implements the ATM Forum User
Network Interface Specification and
the ATM physical layer for Broadband
ISDN according to CCITT
Recommendation I.432.
• Implements the Point-to-Point Protocol
(PPP) over SONET/SDH specification
according to RFC 2615(1619)/1662 of
the PPP Working Group of the Internet
Engineering Task Force (IETF).
• Processes up to two duplex bit-serial
622.08 Mbit/s STS-12 (STM-4) data
streams with on-chip clock and data
recovery and clock synthesis. Each
STS-12 (STM-4) may contain a single
STS-12c (AU-4-4c) or up to four
STS-3c (AU-4).
• Processes up to four duplex bit-serial
155.52 Mbit/s STS-3 (STM-1) data
streams with on-chip clock and data
recovery and clock synthesis. Each
STS-3 (STM-1) may contain a single
STS-3c (AU-4).
• Permits mixed OC-12 and OC-3 data
streams.
• Complies with Telcordia
GR-253-CORE jitter tolerance, jitter
transfer, and intrinsic jitter criteria.
• Provides termination for SONET
Section, Line, and Path overhead or
SDH Regenerator Section, Multiplexer
Section, and High Order Path
overhead.
• Provides cross bar functionality to
swap STS-12 and STS-3 clients
to/from different line-side interfaces.
• Provides support for automatic
protection switching via a 4-bit LVDS
777.6 MHz port.
• Provides cross bar functionality to
swap STS-12 and STS-3 lines and/or
clients to/from different APS interfaces.
• Provides UTOPIA Level 3 32-bit wide
System Interface (clocked up to 104
MHz) with parity support for ATM
applications.
• Provides SATURN® POS-PHY™
Level 3 (32-bit System Interface
(clocked up to 104 MHz) for Packet
over SONET (POS) or ATM
applications.
• Supports independent loop-timed
operation for each transmit serial
stream.
Transmit
FIFO
Transmit
Line
Interface
Receive
FIFO
Receive Analog
Circuitry
Transmit Analog
Circuitry
Clock
Synthesis
Unit
TXD_P/N[4:1]
RXD_P/N[4:1]
SD[4:1]
RCL
K
O
Receive
Line
Interface
LINE_IF PL3/UL3
Transmit
Path
Processor
(4)
Transmit
Path
Trace
Processor
(4)
Transmit
Virtual
Container
Aligner
(4)
Transmit
Regen/
Multiplexor
Processor
(4)
Transmit
Section
Trace
Processor
(4)
Receive
Path
Processor
(4)
Receive
Path
Trace
Processor
(4)
Receive
Virtual
Container
Aligner
(4)
Receive
Regen/
Multiplexor
Processor
(4)
Receive
Section
Trace
Processor
(4) LVDS I/f
(4)
A
P
S
O
_
P
/N
[4
:1
]
SYS
C
L
K
A
PSO
F
P
Bit error
rate mon
(4)
SARC
Alarm Report
Controller (4)
In
band
Alarm
(4)
Transmit
APS
(4)
X-Bar
SONET/APS
REFCLK77_P/N
R
T
O
H
[4
:1
]
SA
L
M
[4
:1
]
RA
L
M
[4
:1
]
B
3
E
[4:
1]
R
T
OH
C
L
K
[4:
1]
R
T
O
H
F
P
[4
:1
]
T
T
O
HE
N[4
:1
]
T
T
O
H
C
L
K
[4:
1]
T
T
O
H
F
P
[4:
1]
T
T
O
H
[4:
1]
PRBS
generator
/ monitor
(4)
UTOPIA L3/
POS-PHY
L3
Transmit
Interface
UTOPIA L3/
POS-PHY
L3
Receive
Interface
TDAT[31:0]
TADR[3:0]
TENB
TSOC/TSOP
TEOP
TMOD[1:0]
TCA/PTPA
TERR
TPRTY
TSX
TFCLK
STPA
RDAT[31:0]
RFCLK
RCA/RVAL
RSX
RMOD[1:0]
RENB
RERR
RSOC/RSOP
REOP
RADR[3:0]
RPRTY
PL3EN
Transmit
ATM/POS
processor
(4)
Receive
ATM/POS
processor
(4)
Receive
channel
Assigner
(4)
Transmit
channel
Assigner
(4)
Transmit
X-Bar
Receive
X-Bar
Microprocessor
Interface
JTAG
Interface
D[1
5
:0
]
A[1
3
:0
]
WRB RD
B
CS
B
IN
T
B
AL
E
RS
T
B
TC
K
TD
I
TMS
TR
S
T
B
TD
O
SD_TEST
AP
SI
F
P
AP
S
I_
P
/N
[4
:1
]
LVDS I/f
(4)
Receive
APS
(4)
X-Bar
BLOCK DIAGRAM