Renesas M306V0T-RPD-E User Manual
Page 36
( 34 / 48 )
7.3 Multiplex Bus (with wait), When Accessing to External Memory Area
Table 7.3 and Figure 7.3 show bus timing when using the memory expansion mode and micropro-
cessor mode (with wait, when accessing to the external memory area).
Table 7.3 Memory expansion mode and microprocessor mode (multiplex bus, with wait)
Address output delay time
Address output hold time (BCLK)
Address output hold time (RD)
Address output hold time (WR)
Chip-select output delay time
Chip-select output hold time (BCLK)
Chip-select output hold time (RD)
Chip-select output hold time (WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK)
Data output hold time (BCLK)
Data output delay time (WR)
Data output hold time (WR)
ALE signal output delay time (BCLK)
ALE signal output hold time (BCLK)
ALE signal output delay time (ADDRESS)
ALE signal output hold time (ADDRESS)
ALE signal output hold time (ADDRESS)
ALE signal output hold time (ADDRESS)
ALE signal output hold time (ADDRESS)
Max.
47
-
-
-
36
-
-
-
38
-
40
-
40
-
-
-
14
-
-
-
-
-
13
Max.
25
-
-
-
25
-
-
-
25
-
25
-
40
-
-
-
25
-
-
-
-
-
8
Symbol
Min.
-
4
(Note 1)
(Note 1)
-
4
(Note 1)
(Note 1)
-
0
-
0
-
4
(Note 1)
(Note 1)
-
-4
(Note 1)
50
0
0
-
Parameter
M306V0EEFP
[ns]
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
td(AD-WR)
tdz(RD-AD)
M306V0T-RPD-E
[ns]
Min.
-
4
(Note 2)
(Note 2)
-
4
(Note 2)
(Note 2)
-
0
-
0
-
4
(Note 2)
(Note 2)
-
-4
(Note 2)
50
0
0
-