Renesas HD49335HNP - Manual (Page 5)

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 5 of 29
Block Diagram
10bit
ADC
AV
SS
VRB VRM VRT
CDS_in
CDS
BLKSH
BLKC
ADC_in
SUB_SW
SUB_PD
STROB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reset
DV
SS
1 to 4
BLKFB
CS
SDATA
SCK
DLL_C
MON
ID
BIAS
Timing
generator
VD_in HD_in CLK_in XSUB CH4 CH3 CH2 CH1 XV4 XV3
PBLK
CPDM
OBP
ADCLK
SP2 SP1
XV2 XV1 1/4clk_o H2A 1/2clk_o H1A RG AV
DD
DV
DD
1 to 4
PGA
DLL
Output latch circuit DC offset
compensation
circuit
Serial
interface
Bias
generator