Ricoh R5C841 - Manual (Page 20)

R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard Data Sheet
12345  2004 R EV . 1.10 3-15
3.3.4 CardBus PC Card Interface signals
Pin Name Type Description
CardBus PC Card Interface Pin Descriptions
CCLK
OUT (TS) CardBus Clock: This signal provides timing for all transactions on the PC Card
Standard interface and it is an input to every PC Card Standard device. All other
CardBus PC Card signals, except CRST# (upon assertion), CCLKRUN#, CINT#,
CSTSCHG, CAUDIO, CCD [2:1]#, and CVS [2:1], are sampled on the rising edge of
CCLK, and all timing parameters are defined with respect to this edge.
CCLKRUN#
I/O
s/h/z
CardBus Clock Run: This signal is used by cards to request starting (or speeding up)
clock; CCLK. CCLKRUN# also indicates the clock status. For PC cards, CCLKRUN# is
an open drain output and it is also an input. The R5C841 indicates the clock status of the
primary bus to the CardBus card.
CRST#
OUT (TS) CardBus Card Reset: This signal is used to bring CardBus Card specific registers,
sequencers and signals to a consistent state. Anytime CRST# is asserted, all CardBus
card output signals will be driven to their begin state.
CAD [31:0]
I/O CardBus Address/Data: These signals are multiplexed on the same CardBus card
pins. A bus transaction consists of an address phase followed by one or more data
phases. CardBus card supports both read and write bursts. CAD [31:0] contains a
physical address (32 bits). For I/O, this is a byte address; for configuration and memory
it is a DWORD address. During data phases, CAD [7:0] contains the east significant byte
(LSB) and CAD [31:24] contains the most significant byte (MSB). Write data is stable
and valid when CIRDY# is asserted and read data is stable and valid when CTRDY# is
asserted. Data is transferred during those clocks where both CIRDY# and CTRDY# are
asserted.
CC/BE [3:0]#
I/O CardBus Command/Bye Enables: These signals are multiplexed on the same
CardBus card pins. During the address phase of a transaction, CC/BE [3:0]# define the
bus command. During the data phase, CC/BE [3:0]# are used as Byte Enables. The Byte
Enables are valid for the entire data phase and determine which byte lanes carry
meaningful data. CC/BE [0]# applies to byte 0 (LSB) and CC/BE [3]# applies to byte 3
(MSB).
CPAR
I/O CardBus Parity: This signal is even parity across CAD [31:0] and CC/BE [3:0]#. All
CardBus card agents require parity generation. CPAR is stable and valid clock after
either CIRDY# is asserted on a write transaction or CTRDY# is asserted on a read
transaction. Once CPAR is valid, it remains valid until one clock after the completion of
the current data phase. (CPAR has the same timing as CAD [31:0] but delayed by one
clock.) The master drives CPAR for address and write data phases; the target drives
CPAR for read data phases.
CFRAME#
I/O
s/h/z
CardBus Cycle Frame: This signal is driven by the current master to indicate the
beginning and duration of a transaction. CFRAME# is asserted to indicate that a bus
transaction is beginning. While CFRAME# is asserted, data transfers continue. When
CFRAME# is deasserted, the transaction is in the final data phase.
CIRDY#
I/O
s/h/z
CardBus Initiator Ready: This signal indicates the initiating agent’s (bus master’s)
ability to complete the current data phase of the transaction. CIRDY# is used in
conjunction with CTRDY#. A data phase is completed on any clock both CIRDY# and
CTRDY# are sampled asserted. During a write, CIRDY# indicates that valid data is
present on CAD [31:0]. During a read, it indicates the master is prepared to accept data.
Wait cycles are inserted until both CIRDY# and CTRDY# are asserted together.
CTRDY#
I/O
s/h/z
CardBus Target Ready: This signal indicates the agent’s (selected target’s) ability to
complete the current data phase of the transaction. CTRDY# is used in conjunction with
CIRDY#. A data phase is completed on any clock both CTRDY# and CIRDY# are
sampled asserted. During a read, CTRDY# indicates that valid data is present on CAD
[31:0]. During a write, it indicates the target is prepared to accept data. Wait cycles are
inserted until both CIRDY# and CTRDY# are asserted together.
CSTOP#
I/O
s/h/z
CardBus Stop: This signal indicates the current target is requesting the master to stop
the current transaction.
CDEVSEL#
I/O
s/h/z
CardBus Device Select: This signal indicates the driving device has decoded its
address as the target of the current access when actively driven. As an input,
CDEVSEL# indicates whether any device on the bus has been selected.
CREQ#
IN CardBus Request: This signal indicates to the arbiter that this agent desires use of the
bus. Every master has its own CREQ#.