Rowe ISP1362 OTG add-on eval kit with Intel PXA250/255 IDP rev. 4 UM10032 - Manual (Page 16)

For DMA accesses, use the following address ranges. This will generate the DMA Acknowledge signals needed. Processor uses CS2#.
User ma
nual
UM10
032
_4
PIO Address Map: 0000 0000h to 00FF FFFFh.
DMA Channel 0 Address Map: 0200 0000h to 02FF FFFFh.
DMA Channel 1 Address Map: 0100 0000h to 01FF FFFFh.
Fig 14. USB OTG and host connectors – part 1 (page 5)
ISP1362 OT
G add-o
n ev
al kit with Intel PXA250/2
55 IDP rev. 4
UM10032
Rev. 04 —
12 Octob
er 2009
16 of
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© ST
-E
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SSO
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er
ved.