Texas Instruments TMS320C642X User Manual
User's guide
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Table of contents
Document Outline
- TMS320C642x DSPInter-Integrated Circuit (I2C) Peripheral
- Table of Contents
- Preface
- 1 Introduction
- 2 Peripheral Architecture
- 2.1 Bus Structure
- 2.2 Clock Generation
- 2.3 Clock Synchronization
- 2.4 Signal Descriptions
- 2.5 START and STOP Conditions
- 2.6 Serial Data Formats
- 2.7 Endianness Considerations
- 2.8 Operating Modes
- 2.9 NACK Bit Generation
- 2.10 Arbitration
- 2.11 Reset Considerations
- 2.12 Initialization
- 2.13 Interrupt Support
- 2.14 DMA Events Generated by the I2C Peripheral
- 2.15 Power Management
- 2.16 Emulation Considerations
- 3 Registers
- 3.1 I2C Own Address Register (ICOAR)
- 3.2 I2C Interrupt Mask Register (ICIMR)
- 3.3 I2C Interrupt Status Register (ICSTR)
- 3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH)
- 3.5 I2C Data Count Register (ICCNT)
- 3.6 I2C Data Receive Register (ICDRR)
- 3.7 I2C Slave Address Register (ICSAR)
- 3.8 I2C Data Transmit Register (ICDXR)
- 3.9 I2C Mode Register (ICMDR)
- 3.10 I2C Interrupt Vector Register (ICIVR)
- 3.11 I2C Extended Mode Register (ICEMDR)
- 3.12 I2C Prescaler Register (ICPSC)
- 3.13 I2C Peripheral Identification Register (ICPID1)
- 3.14 I2C Peripheral Identification Register (ICPID2)
- Appendix A Revision History