Texas Instruments UCC2977EVM User Manual
Page 18
Burst Dimming
2-4
2.7
Burst Dimming
Burst dimming can be implemented at the OPEN/SD pin at the cost of
open-lamp detection.
Connect pin 2 to pin 3 of JP1 to disable the open-lamp detection circuit during
burst dimming mode.
Since the feedback loop does not need to operate with minimum lamp current
(as with analog dimming), the feedback capacitor, C4, can be reduced to 22
nF to improve the response time when the lamp restrikes.
To implement burst dimming on the EVM, AD should be grounded to set
maximum lamp brightness. A low-frequency 0 V – 4 V square wave applied
to BD will modulate the lamp current between zero and full intensity at the
desired frequency. A low-frequency repetition rate greater than 120 Hz is
recommended to avoid visible flicker. Applying 5 V at BD forces the lamp
current to zero, where 0 V at BD will force maximum lamp current. The duty
cycle of the square wave determines the lamp brightness as a percent of rated
lamp current.
2.8
Clamp Circuit (Optional)
There is also a clamp circuit to limit the maximum secondary voltage.
This circuit is typically not needed since the CCFL strikes or the open-lamp
circuit triggers before destructive levels are reached.
If R5 and Q1 are added to the board, the peak clamp voltage for the EVM is
given by equation (6):
Since the feedback loop does not need to operate with minimum lamp current
(as with analog dimming), the feedback capacitor, C4, can be reduced to 22
nF to improve the response time when the lamp restrikes.
V
CLAMP
+
ǒ
1.5 V
)
V
be
Ǔ
(R7
)
R8
)
R9
)
R11
)
R14
)
R16
)
R17
)
R18
)
R6
)
R4)
R4
PEAK
(6)
The peak clamped voltage for the evaluation board is 2200V.
The evaluation board components can be modified depending on the
application requirements. A supply between 3 Vdc and 6 Vdc is required for
this board to operate a 270~450 V cold-cathode fluorescent lamp (CCFL) from
1 mA to 4.8 mA. The input voltage range changes with different voltage lamp.