Texas Instruments TMS320C645X - Manual (Page 11)

Overview
11 General-Purpose Input/Output (GPIO) SPRU724
Figure 2. GPIO Peripheral Block Diagram
DIR
SET_DATA
OUT_DATA
CLR_DATA
Synchronization
logic
Peripheral clock
(CPU/6)
Direction
Set
data
Output
data
Clear
data
IN_DATA
Input
data
Edge detection
logic
Interrupt and
EDMA event
(GPINTn
‡ )
SET_RIS_TRIG
RIS_TRIG §
CLR_RIS_TRIG
CLR_FAL_TRIG
SET_FAL_TRIG
FAL_TRIG §
Data input/output
EDMA event and interrupt
generation
Set rising
edge trigger
Rising edge
trigger
Clear rising
edge trigger
Set falling
edge trigger
Falling edge
trigger
Clear falling
edge trigger
GPn †
GPIO peripheral
† Some of the GPn pins are MUXed with other device signals. Refer to the device-specific datasheet for details.
‡ All GPINTn can be used as CPU interrupts and synchronization events to the EDMA controller.
§ The RIS_TRIG and FAL_TRIG registers are internal to the GPIO module and are not visible to the CPU.