Texas Instruments DM648 DSP - Manual (Page 32)

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CK
CK
CKE
CS
WE
RAS
CAS
DM
DQS
BA[2:0]
A[13:0]
DQ[7:0]
VREF
DDR2
memory
x8−bit
DQS
RDQS
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_WE
DDR_RAS
DDR_DQM0
DDR_CAS
DDR_DQS0
DDR_DQS0
DDR_BA[2:0]
DDR_A[13:0]
DDR_D[7:0]
DDR_DQM1
DDR_DQS1
DDR_D[15:8]
DDR_VREF
DDR2
memory
controller
ODT
DDR_ODT0
DDR_ODT1
DDR_DQS1
memory
x8−bit
DQS
A[13:0]
VREF
ODT
DQ[7:0]
RDQS
BA[2:0]
RDQS
DQS
DM
RAS
CAS
WE
CS
CKE
CK
CK
DDR2
VREF RDQS
DDR_DQGATE0 (A)
DDR_DQGATE1 (A)
DDR_DQGATE2 (A)
DDR_DQGATE3 (A)
Using the DDR2 Memory Controller
Figure 19. Connecting to Two 8-Bit DDR2 SDRAM Devices
A These pins are used as a timing reference during memory reads. For routing rules, see the device-specific data
manual.
DSP DDR2 Memory Controller 32 SPRUEK5A – October 2007
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