Memory manager, Block mapping, Code initialization – Xilinx XAPP169 User Manual
Page 14: Xilinx spartan- ii fpga
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XAPP169 (v1.0) November 24, 1999
1-800-255-7778
MP3 NG: A Next Generation Consumer Platform
R
The reference code that was developed for the standard is available from the Fraunhofer
Institute at the following URL:
A commercial decoder is available from Xaudio. Information on the Xaudio product line is
available from:
Memory Manager
The Memory Manager handles the tasks required to mask NAND FLASH issues from the other
software in the system. Specifically these tasks are block mapping and code initialization.
Block Mapping
This involves maintaining a table of valid FLASH blocks and configuring the MMU to map them
into a linear address space. For the FLASH memory space the TLB entries are set to the same
8 KB size to match the block size of the FLASH itself, and the entries are not locked in the TLB.
A single TLB entry is used to map the SDRAM memory space. This entry is configured to map
a 4 MB memory space and is locked in the TLB.
In the event that an error is detected in a valid block, this code is also responsible for copying
the data to an unused block and marking the block in which the error was detected as bad.
Code Initialization
This function copies the code image from FLASH to RAM at boot time. This routine must also
perform error detection on the image as it is copied. If an error is detected, error correction must
be performed and the block mapping code informed.
Xilinx
Spartan- II
FPGA
shows the architecture implemented in the Spartan-II device for this application. It
consists of eight major functional blocks:
• IP Bus Controller
• CPU Interface
• LCD Controller
• Memory Datapath
• SDRAM Controller
• FLASH Controller
• CompactFlash Controller
• IRDA Controller
• DAC Interface
• Touch Screen Interface
These blocks are interconnected by a simple non-multiplexed, multi-master, address data bus
that is referred to as the IP bus. While the IP bus may appear to be a bus to the function blocks,
it is not a bus at all but instead uses multiplexers for gating data into the internal datapaths. This
approach eliminates the need for 3-state drivers within the design. In this implementation the
bus has two masters; the CPU Interface and the LCD Controller.
shows a top level
block diagram of the FPGA.