Xilinx LogiCORE IP CAN 3.2 - Manual (Page 27)

CAN Getting Started Guide www.xilinx.com 27
UG186 April 19, 2010
Demonstration Test Bench
• After the fourth message is transmitted and received, the Interrupt Enable Register is
written to enable interrupts for TXOK, RXOK and TXBFLL. This register is read from
and the value read is compared with the value written.
•
The fifth message does not pass acceptance filtering. Only the TXOK bit in the ISR is
set when the ISR is asserted.
Customizing the Demonstration Test Bench
This section describes the variety of demonstration test bench customization options that
can be used for individual system requirements.
Changing the Data
You can change the contents of the message written to the TX FIFO / TX HPB by changing
the procedure call that writes to the TX FIFO and the TX HPB memory locations. The
relevant fields in the checkers must also be changed to ensure that the message read from
the RX FIFO matches the message that was transmitted.
Changing the CAN Parameters
The values written to the BRPR and the BTR registers can be changed for appropriate bit
timing values. The test bench operates in the Loop Back mode of operation.
Changing the Test Bench Structure
You can add messages using the following steps.
1. Write the message to the TX FIFO.
2. Wait for an interrupt and process the interrupt.
3. Read the received message from the RX FIFO.