Xilinx Virtex-5 FPGA ML561 - Manual (Page 47)

Virtex-5 FPGA ML561 User Guide www.xilinx.com 47
UG199 (v1.2.1) June 15, 2009
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Chapter 5
Signal Integrity Recommendations
Termination and Transmission Line Summaries
The following are common recommendations for the signal termination scheme to all
external memories implemented on the Virtex-5 FPGA ML561 Development Board:
• Single-ended signals : Simulation indicates that for a single-ended signal, there is no
significant performance difference for a signal with split termination of 100
Ω + 100Ω
between V
DD
and GND versus the V
TT
termination of 50 Ω to the V
REF
voltage.
Because the power consumption for the split termination is considerably higher than
the V
TT
termination for the SSTL2, SSTL18, and HSTL I/O standards, V
TT
termination
is recommended for single-ended signals on the board, such as data, address, and
control. For bidirectional single-ended signals (for example, DDR2 DQ), the V
TT
termination is provided at both ends of the signal at the FPGA as well as at the
memory.
•
Differential signals : For differential pair signals, a 100 Ω differential termination is
provided between the two legs of the differential pair. This termination is placed
closest to the load. For bidirectional differential signals (for example, DDR2 DQS), the
differential SelectIO™ primitives in Virtex-5 FPGAs (for example,
DIFF_SSTL_II_18_DCI), account for the differential termination within the IOB. So
external differential termination is required only at the memory.
• Multiload signals : Address and control signals are driven by the FPGA, and they
have multiple loads. The termination is placed at the end of the trace after the last
load.
Table 5-1 through Table 5-5 summarize the specific termination schemes used on the
Virtex-5 FPGA ML561 Development Board for the following five different memory
interfaces. For each signal category, these tables include reference to the preliminary IBIS
simulation results
(1) .
1. DDR400 SDRAM Components ( Table 5-1 )
2. DDR2 SDRAM DIMM ( Table 5-2 )
3. DDR2 SDRAM Components ( Table 5-3 )
4. QDRII SRAM ( Table 5-4 )
5. RLDRAM II ( Table 5-5 )
1. Virtex-4 device IBIS models were used during the development of the ML561 board to understand the
expected signal integrity of the memory interface signals. When the Virtex-5 device IBIS models are available,
the results of post-layout IBIS simulations and characterization results will be reported.