P400 series, Vishay high power products, Passivated assembled circuit elements, 40 a – C&H Technology P400 Series User Manual

Page 3: On-state conduction, Blocking

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Document Number: 93755

2

Revision: 05-Nov-09

P400 Series

Vishay High Power Products

Passivated Assembled

Circuit Elements, 40 A

ON-STATE CONDUCTION

PARAMETER SYMBOL

TEST

CONDITIONS

VALUES

UNITS

Maximum DC output current
at case temperature

I

O

Full bridge circuits

40

A

80

°C

Maximum peak, one-cycle
non-repetitive on-state or
forward current

I

TSM

,

I

FSM

t = 10 ms

No voltage
reapplied

Sinusoidal half wave,
initial T

J

= T

J

maximum

385

A

t = 8.3 ms

400

t = 10 ms

100 % V

RRM

reapplied

325

t = 8.3 ms

340

Maximum I

2

t for fusing

I

2

t

t = 10 ms

No voltage
reapplied

745

A

2

s

t = 8.3 ms

680

t = 10 ms

100 % V

RRM

reapplied

530

t = 8.3 ms

480

Maximum I

2

√t for fusing

I

2

√t

t = 0.1 ms to 10 ms, no voltage reapplied
I

2

t for time tx = I

2

√t · √tx

7450

A

2

√s

Low level value of threshold voltage

V

T(TO)1

(16.7 % x

π x I

T(AV)

< I <

π x I

T(AV)

), T

J

= T

J

maximum

0.83

V

High level value of threshold voltage

V

T(TO)2

(I >

π x I

T(AV)

), T

J

= T

J

maximum

1.03

Low level value of on-state slope resistance

r

t1

(16.7 % x

π x I

T(AV)

< I <

π x I

T(AV)

), T

J

= T

J

maximum

9.61

m

Ω

High level value of on-state slope resistance

r

t2

(I >

π x I

T(AV)

), T

J

= T

J

maximum

7.01

Maximum on-state voltage drop

V

TM

I

TM

=

π x I

T(AV)

T

J

= 25 °C

1.4

V

Maximum forward voltage drop

V

FM

I

FM

=

π x I

F(AV)

Maximum non-repetitive rate of rise of
turned-on current

dI/dt

T

J

= 125 °C from 0.67 V

DRM

I

TM

=

π x I

T(AV)

, I

g

= 500 mA, t

r

< 0.5 μs, t

p

> 6 μs

200

A/μs

Maximum holding current

I

H

T

J

= 25 °C anode supply = 6 V, resistive load

130

mA

Maximum latching current

I

L

250

BLOCKING

PARAMETER SYMBOL

TEST

CONDITIONS VALUES

UNITS

Maximum critical rate of rise of
off-state voltage

dV/dt

T

J

= 125 °C, exponential to 0.67 V

DRM

gate open

200

V/μs

Maximum peak reverse and off-state
leakage current at V

RRM

, V

DRM

I

RRM

,

I

DRM

T

J

= 125 °C, gate open circuit

10

mA

Maximum peak reverse leakage current

I

RRM

T

J

= 25 °C

100

μA

RMS isolation voltage

V

ISOL

50 Hz, circuit to base, all terminals shorted,
T

J

= 25 °C, t = 1 s

2500

V

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