Rainbow Electronics MAX17083 User Manual
Page 13
MAX17083
Low-Voltage, Internal Switch,
Step-Down Regulator
______________________________________________________________________________________
13
Additionally, an additional feedback pole—capacitor
from FB to analog ground (C
FB
)—might be necessary to
cancel the unwanted ESR zero of the output capacitor.
In general, if the ESR zero occurs before the Nyquist
pole, then canceling the ESR zero is recommended.
If:
Then:
where R
FB
is the parallel impedance of the FB resistive
divider.
SMPS Output Ripple Voltage
With polymer capacitors, the effective series resistance
(ESR) dominates and determines the output ripple volt-
age. The step-down regulator’s output ripple voltage
(V
RIPPLE
) equals the total inductor ripple current
(
ΔI
INDUCTOR
) multiplied by the output capacitor’s ESR.
Therefore, the maximum ESR to meet the output ripple
voltage requirement is:
where f
SW
is the switching frequency. The actual capa-
citance value required relates to the physical case size
needed to achieve the ESR requirement, as well as to
the capacitor chemistry. Thus, polymer capacitor selec-
tion is usually limited by ESR and voltage rating rather
than by capacitance value. Alternatively, combining
ceramics (for the low ESR) and polymers (for the bulk
capacitance) helps balance the output capacitance vs.
output ripple voltage requirements.
Internal SMPS Transient Response
The load-transient response depends on the overall out-
put impedance over frequency, and the overall amplitude
and slew rate of the load step. In applications with large,
fast load transients (load step > 80% of full load and slew
rate > 10A/µs), the output capacitor’s high-frequency
response—ESL and ESR—needs to be considered. To
prevent the output voltage from spiking too low under a
load-transient event, the ESR is limited by the following
equation (ignoring the sag due to finite capacitance):
where V
STEP
is the allowed voltage drop,
ΔI
LOAD(MAX)
is
the maximum load step, and R
PCB
is the parasitic board
resistance between the load and output capacitor.
The capacitance value dominates the midfrequency
output impedance and continues to dominate the load-
transient response as long as the load transient’s slew
rate is fewer than two switching cycles. Under these
conditions, the sag and soar voltages depend on the
output capacitance, inductance value, and delays in
the transient response. Low inductor values allow the
inductor current to slew faster, replenishing charge
removed from or added to the output filter capacitors
by a sudden load step, especially with low differential
voltages across the inductor. The sag voltage (V
SAG
)
that occurs after applying the load current can be esti-
mated by the following:
where D
MAX
is the maximum duty factor (see the
Electrical Characteristics
table), T is the switching period
(1/f
OSC
), and
ΔT equals V
OUT
/V
IN
x T when in PWM
mode, or L x I
IDLE
/(V
IN
- V
OUT
) when in pulse-skipping
mode. The amount of overshoot voltage (V
SOAR
) that
occurs after load removal (due to stored inductor energy)
can be calculated as:
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V
SOAR
from causing problems during
load transients. Generally, once enough capacitance is
added to meet the overshoot requirement, undershoot at
the rising load edge is no longer a problem.
Input-Capacitor Selection
The input capacitor must meet the ripple current
requirement (I
RMS
) imposed by the switching currents.
The I
RMS
requirements of the regulator can be deter-
mined by the following equation:
The worst-case RMS current requirement occurs when
operating with V
IN
= 2V
OUT
. At this point, the above
equation simplifies to I
RMS
= 0.5 x I
LOAD.
I
I
V
V
V
V
RMS
LOAD
IN
OUT
IN
OUT
=
⎛
⎝⎜
⎞
⎠⎟
(
)
-
V
I
L
C
V
SOAR
LOAD MAX
OUT OUT
≈
(
)
Δ
(
)
2
2
V
L
I
C
V
D
V
I
SAG
LOAD MAX
OUT
IN
MAX
OUT
=
(
)
×
(
)
+
Δ
Δ
(
)
2
2
-
L
LOAD MAX
OUT
T
T
C
(
)
-
Δ
(
)
R
V
I
R
ESR
STEP
LOAD MAX
PCB
≤
⎛
⎝
⎜
⎞
⎠
⎟
Δ
(
)
-
R
V f
L
V
V
V
V
ESR
IN SW
IN
OUT
OUT
RIPPLE
≤
(
)
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
-
C
C
ESR
R
FB
OUT
FB
>
⎛
⎝⎜
⎞
⎠⎟
ESR
D
f
C
SW
OUT
>
+
⎛
⎝⎜
⎞
⎠⎟
1
4
π