Svi applications information – Rainbow Electronics MAX17480 User Manual
Page 43
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
______________________________________________________________________________________
43
The capacitance value required is determined primarily
by the stability requirements. However, the soar and
sag calculations are still provided here for reference.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from or added to
the output filter capacitors by a sudden load step.
Therefore, the amount of output soar and sag when the
load is applied or removed is a function of the output
voltage and inductor value. The soar and sag voltages
are calculated as:
:
where D
MAX
is the maximum duty cycle of the NB
SMPS as listed in the
Electrical Characteristics
table,
t
SW3
is the NB switching period programmed by the
OSC pin, and
∆t equals V
OUT
/V
IN
x t
SW
when in forced-
PWM mode, or L x I
LX3MIN
/(V
IN
- V
OUT
) when in pulse-
skipping mode.
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V
SOAR
from causing problems during
load transients. Generally, once enough capacitance is
added to meet the overshoot requirement, undershoot at
the rising load edge is no longer a problem.
NB Input Capacitor Selection
The input capacitor must meet the ripple-current require-
ment (I
RMS
) imposed by the switching currents. The I
RMS
requirements can be determined by the following equation:
:
The worst-case RMS current requirement occurs when
operating with V
IN3
= 2V
OUT3
. At this point, the above
equation simplifies to I
RMS
= 0.5 x I
LOAD3
.
For most applications, nontantalum chemistries
(ceramic, aluminum, or OS-CON) are preferred due to
their resistance to inrush surge currents typical of sys-
tems with a mechanical switch or connector in series
with the input. The MAX17480 NB regulator is operated
as the second stage of a two-stage power-conversion
system. Tantalum input capacitors are acceptable.
Choose an input capacitor that exhibits less than 10
°C
temperature rise at the RMS input current for optimal
circuit longevity.
NB Steady-State Voltage Positioning
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the out-
put capacitance and processor’s power-dissipation
requirements. For NB, the load line is generated by
sensing the inductor current through the high-side
MOSFET on-resistance (R
ON(NH3)
), and is internally
preset to -5.5mV/A (typ). This guarantees the output
voltage to stay in the static regulation window over the
maximum load conditions per AMD specifications. See
Table 6 for full-load voltage droop according to differ-
ent ILIM3 settings.
NB Transient Droop and Stability
The voltage-positioned load-line of the NB SMPS also
provides the AC ripple voltage required for stability. To
maintain stability, the output capacitive ripple must be
kept smaller than the internal AC ripple voltage. Hence,
a minimum NB output capacitance is required as calcu-
lated below:
:
where R
DROOP3(MIN)
is 4mV/A as defined in the
Electrical Characteristics
table, and f
SW3
is the NB
switching frequency programmed by the OSC pin.
SVI Applications Information
I
2
C Bus-Compatible Interface
The MAX17480 is a receive-only device. The 2-wire seri-
al bus (pins SVC and SVD) is designed to attach on a
low-voltage I
2
C-like bus. In the AMD mobile application,
the CPU directly drives the bus at a speed of 3.4MHz.
The CPU has a push-pull output driving to the V
DDIO
voltage level. External pullup resistors are not required.
When not used in the specific AMD application, the ser-
ial interface can be driven to as high as 2.5V, and can
operate at the lower speeds (100kHz, 400kHz, or
1.7MHz). At lower clock speeds, external pullup resis-
tors can be used for open-drain outputs. Connect both
SVC and SVD lines to V
DDIO
through individual pullup
resistors. Calculate the required value of the pullup
resistors using:
:
where t
R
is the rise time, and should be less than 10% of
the clock period. C
BUS
is the total capacitance on the bus.
The MAX17480 is compatible with the standard SVI inter-
face protocol as defined in the following subsections.
Figure 12 shows the SVI bus START, STOP, and data
change conditions.
R
t
PULLUP
R
≤
C
BUS
C
f
R
V
V
OUT
SW
DROOP MIN
OUT
IN
3
3
3
3
3
1
2
1
>
Ч
Ч
+
⎛
⎝⎜
⎞
⎠⎟
(
)
I
I
V
V
V
V
RMS
LOAD
IN
OUT
IN
OUT
=
⎛
⎝
⎜
⎞
⎠
⎟
−
(
)
3
3
3
3
3
V
I
L
V
C
V
I
SOAR
LOAD MAX
OUT
OUT
SAG
3
3
2
3
3
3
3
2
=
(
)
=
∆
∆
(
)
L
LOAD MAX
OUT
IN
MAX
OUT
L
C
V
D
V
I
3
2
3
3
3
3
2
(
)
(
)
×
−
(
)
+
∆
L
LOAD MAX
SW
OUT
t
t
C
3
3
3
(
)
−
(
)
∆