Electrical characteristics (continued) – Rainbow Electronics MAX16825 User Manual

Page 3

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MAX16824/MAX16825

High-Voltage, Three-Channel Linear

High-Brightness LED Drivers

_______________________________________________________________________________________

3

ELECTRICAL CHARACTERISTICS (continued)

(V

IN

= 12V, C

REG

= 1µF to GND, I

REG

= 0, R

CS_

= 2Ω from CS_ to GND, T

J

= T

A

= -40°C to +125°C, unless otherwise noted. Typical

values are at T

J

= T

A

= +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

OUTPUTS (OUT1, OUT2, OUT3)

Turn-On Time

t

R

PWM_ rising time, t

R

, is measured from 20%

to 80% of I

OUT

1

µs

Turn-Off Time

t

F

PWM_ falling time, t

F

, is measured from

80% to 20% of I

OUT

1

µs

SPI INTERFACE (CLK, LE,

OE, DIN, DOUT) (Figures 3 and 4)

DIN, CLK, LE, OE Input Bias
Current

DIN = CLK = LE = OE = 0 or 5V

1

µA

DIN, CLK, LE, OE Input-Voltage
High

V

IH

2.2

V

DIN, CLK, LE, OE Input-Voltage
Low

V

IL

0.5

V

CLK Clock Period

t

CP

50% of CLK rising to 50% of next CLK
rising, Figure 3

50

ns

CLK Pulse-Width High

t

CH

50% of CLK rising to 50% of CLK falling,
Figure 3

24

ns

CLK Pulse-Width Low

t

CL

50% of CLK falling to 50% of CLK rising,
Figure 3

24

ns

DIN Setup Time

t

DS

50% of DIN rising to 50% of CLK rising,
Figure 3

5

ns

DIN Hold Time

t

DH

50% of CLK rising to 50% of DIN falling,
Figure 3

10

ns

DOUT Propagation Delay

t

DO

50% of CLK rising to 50% of DOUT rising/
falling, Figure 3

5

ns

DOUT Rise/Fall Time

t

DR

/t

DF

C

DOUT

= 10pF, 10% to 90% of DOUT

rising/falling edge (Note 6)

15

ns

DOUT Voltage High

V

DOH

I

SOURCE

= 4mA

4.5

V

DOUT Voltage Low

V

DOL

I

SINK

= 4mA

0.5

V

LE Pulse-Width High

t

LW

50% of LE rising to 50% of LE falling,
Figure 3

20

ns

LE Setup Time

t

LS

50% of CLK rising to 50% of LE rising,
Figure 3

15

ns

LE Rising to OUT_ Rising Delay

t

LRR

50% of LE rising to 50% of OUT_ rising,
Figure 4

150

ns

LE Rising to OUT_ Falling Delay

t

LRF

50% of LE rising to 50% of OUT_ falling,
Figure 4

475

ns

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