Design procedure – Rainbow Electronics MAX8712 User Manual

Page 19

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Design Procedure

Linear Regulator

Output-Voltage Selection

Adjust the linear-regulator output voltage by connecting
a resistive voltage-divider from the linear-regulator out-
put AVDD to GND with the center tap connected to FBL
(Figure 1). Select the lower resistor of the divider R2 in
the range of 10kΩ to 50kΩ. Calculate the upper resistor
R1 with the following equation:

where V

FBL

= 2.5V (typ) is the regulation point of the

linear regulator.

Input-Capacitor Selection

The linear regulator’s output stage consists of a PNP pass
transistor. Rapid movements of the input voltage must be
avoided since the movement can be coupled into the
base of the transistor through the base-to-emitter junction
capacitance. The input capacitor reduces the current
peaks drawn from the input supply and slows down the
input voltage movement. One 10µF ceramic capacitor is
used in the Typical Operating Circuits (Figure 1, 2, and 3)
because of the high source impedance seen in typical
lab setups. Actual applications usually have much lower
source impedance, since the linear regulator typically
runs directly from the output of another regulated supply
and can operate with less input capacitance.

Output-Capacitor Selection

The output capacitor and its equivalent series resistance
(ESR) affect the linear regulator’s stability and transient
response. The regulator can deliver at least 300mA out-
put current continuously with a 4.7µF output capacitor.

The typical load on the linear regulator for source-driver
applications is a large pulsed load, with a peak current
of approximately 1A and pulse width of approximately
2µs. The shape of the pulse is close to a triangle, so it
is equivalent to a square pulse with 1A height and 1µs
pulse width. The total voltage dip during the pulsed
load transient also has two components: the ohmic dip
due to the output capacitor’s ESR, and the capacitive
dip caused by discharging the output capacitance:

where I

PULSE

is the height of the pulse load, and t

PULSE

is the pulse width. Higher capacitance and lower ESR
result in less voltage dip. The ESR dip can be ignored
when using ceramic output capacitors. Calculate the
minimum required capacitance for the maximum allowed
dip using:

The above equations are “worst-case” and assume that
the linear regulator does not react to correct the output
voltage during the load pulse. In fact, the regulator is
fast enough to partially correct the output voltage, so
the actual dip may be smaller, or a smaller capacitor
may be acceptable. For the typical load pulse
described above, assuming the voltage dip must be
limited to 150mV, the minimum output capacitor is:

Because the regulator is able to limit the dip somewhat,
the circuit of Figure 1 uses a 4.7µF output capacitor.
The voltage rating and temperature characteristics of
the output capacitor must also be considered.

Feed-Forward Compensation

The output capacitance and equivalent load resistance
determine the dominant pole. An internal parasitic
capacitance of the regulator creates a second pole.
This pole typically occurs at 100kHz, but can vary
between 60kHz and 140kHz depending on the process
variation. Since the pole occurs after the loop gain
crossover, it does not affect the loop stability. However,
canceling this pole with an additional zero can improve
the load-transient response.

A zero can be added by connecting a feed-forward
capacitor (C1) between OUTL and FBL as shown in
Figure 1. The frequency of the zero can be calculated
with the following equation:

where R1 is the upper resistor of the feedback divider.
To cancel the second pole, the zero should be placed
at or below the frequency of the second pole. Because
the frequency of the second pole varies between
60kHz and 140kHz, the zero can be placed between
40kHz and 60kHz.

f

R

C

ZERO

=

Ч

Ч

1

2

1

1

π

C

A

s

V

F

OUT MIN

(

)

.

.

×

=

1

1

0 15

6 7

µ

µ

C

I

t

V

OUT MIN

PULSE

PULSE

DIP MAX

(

)

(

)

×

V

V

V

V

I

R

V

I

t

C

DIP

DIP ESR

DIP C

DIP ESR

PULSE

ESR

DIP C

PULSE

PULSE

OUT

(

)

( )

(

)

( )

=

+

=

Ч

Ч

R

R

V

V

AVDD

FBL

1

2

1

=

×

MAX8710/MAX8711/MAX8712

Low-Cost Linear-Regulator

LCD Panel Power Supplies

______________________________________________________________________________________

19

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