Rainbow Electronics MAX5548 - Manual (Page 10)

MAX5548
Early STOP Conditions
The MAX5548 recognizes a STOP condition at any point
during transmission except if a STOP condition occurs in
the same high pulse as a START condition (
Figure 4).
This condition is not allowed in the I 2 C format.
Repeated START Conditions
A repeated START (S r ) condition is used when the bus
master is writing to several I 2 C devices and does not
want to relinquish control of the bus. The MAX5548’s
serial interface supports continuous write operations
with an S
r condition separating them.
Acknowledge Bit (ACK)
Successful data transfers are acknowledged with an
acknowledge bit (ACK). Both the master and the
MAX5548 (slave) generate acknowledge bits. To gen-
erate an acknowledge, the receiving device must pull
SDA low before the rising edge of the acknowledge-
related clock pulse (ninth pulse) and keep it low during
the high period of the clock pulse (Figure 5).
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the master should reattempt com-
munication at a later time.
Slave Address
A master initiates communication with a slave device
by issuing a START condition followed by a slave
address (see Table 3). The slave address consists of 7
Dual, 8-Bit, Programmable, 30mA
High-Output-Current DAC
10 ______________________________________________________________________________________
S P Sr
SCL
SDA
Figure 3. START and STOP Conditions
SCL
SDA
STOP START
SCL
SDA
ILLEGAL
STOP
START
ILLEGAL EARLY STOP CONDITION
LEGAL STOP CONDITION
Figure 4. Early STOP Conditions
SCL
SDA
S
P Sr
t
SU:DAT
t HD:DAT
t
RDA
t RCL
t FCL
t HIGH
t LOW t HIGH t LOW
t FCL
t RCL
t SU:STO t HD:STA
t FDA
t SU:STA
Figure 2. I 2 C Serial-Interface Timing Diagram