Rainbow Electronics ADC12041 - Manual (Page 23)

Features and Operating Modes
(Continued)
If the settling time of the source is greater than 500 ns the
acquisition time should be about 300 ns longer than the
settling time for a ‘‘well-behaved’’ smooth settling charac-
teristic
FULL CALIBRATION CYCLE
A full calibration cycle compensates for the ADC’s linearity
and offset errors The converter’s DC specifications are
guaranteed only after a full calibration has been performed
A full calibration cycle is initated by writing a Ful-Cal com-
mand to the ADC12041 During a full calibration the offset
error is measured eight times averaged and a correction
coefficient is created The offset correction coefficient is
stored in an internal offset correction register
The overall linearity correction is achieved by correcting the
internal DAC’s capacitor mismatches Each capacitor is
compared eight times against all remaining smaller value
capacitors The errors are averaged out and correction co-
efficients are created
Once the converter has been calibrated an arithmetic logic
unit (ALU) uses the offset and linearity correction coeffi-
cients to reduce the conversion offset and linearity errors to
within guaranteed limits
AUTO-ZERO CYCLE
During an auto-zero cycle the offset is measured only once
and a correction coefficient is created and stored in an inter-
nal offset register An auto-zero cycle is initiated by writing
an Auto-Zero command to the ADC12041
DIGITAL INTERFACE
The digital control signals are CS RD WR and RDY Specif-
ic timing relationships are associated with the interaction of
these signals Refer to the Digital Timing Diagrams section
for detailed timing specifications The active low RDY signal
indicates when a certain event begins and ends It is recom-
mended that the ADC12041 should only be accessed when
the RDY signal is low It is in this state that the ADC12041 is
ready to accept a new command This will minimize the ef-
fect of noise generated by a switching data bus on the ADC
The only exception to this is when the ADC12041 is in the
standby mode at which time the RDY is high
The
ADC12041 is in the standby mode at power up or when a
STANDBY command is issued A Ful-Cal Auto-Zero Reset
or Start command will get the ADC12041 out of the standby
mode This may be observed by monitoring the status of the
RDY signal
The RDY signal will go low when the
ADC12041 leaves the standby mode
The following describes the state of the digital control sig-
nals for each programmed event in both 8-bit and 13-bit
mode RDY should be low before each command is issued
except for the case when the device is in standby mode
FUL-CAL OR AUTO-ZERO COMMAND
8-bit mode A Ful-Cal or Auto-Zero command must be is-
sued and the BW bit (b
3
) cleared The active edge of the
write pulse on the WR pin will force the RDY signal high At
this time the converter begins executing a full calibration or
auto-zero cycle The RDY signal will automatically go low
when the full calibration or auto-zero cycle is done
13-bit mode A Ful-Cal or Auto-Zero command must be is-
sued and the BW bit (b 3 ) set The active edge of the write
pulse on the WR pin will force the RDY signal high At this
time the converter begins executing a full calibration or
auto-zero cycle The RDY signal will automatically go low
when the full calibration or auto-zero cycle is done
STARTING A CONVERSION START COMMAND
In order to completely describe the events associated with
the Start command both the SYNC-OUT and SYNC-IN
modes must be considered
SYNC-OUT Asynchronous
8-bit mode
A write to the ADC12041 should set the acquisi-
tion time clear the BW and SYNC bit and select the START
command in the Configuration register In order to initiate a
conversion
two reads must be performed from the
ADC12041 The rising edge of the second read pulse will
force the RDY pin high and begin the programmed acquisi-
tion time selected by bits b
1
and b
0
of the Configuration
register The SYNC pin will go high indicating that a conver-
sion sequence has begun following the end of the acquisi-
tion period The RDY and SYNC signal will fall low when the
conversion is done At this time new information such as a
new acquisition time and operational command can be writ-
ten into the Configuration register or it can remain un-
changed Assuming that the START command is in the
Configuration register the previous conversion can be read
The first read places the lower byte of the conversion result
contained in the Data register on the data bus The second
read will place the upper byte of the conversion result
stored in the Data register on the data bus The rising edge
on the second read pulse will begin another conversion se-
quence and raise the RDY and SYNC signals appropriately
13-bit mode The acquisition time should be set the BW bit
set the SYNC bit cleared and the START command issued
with a write to the ADC12041 In order to initiate a conver-
sion a single read must be performed from the ADC12041
The rising edge of the read signal will force the RDY signal
high and begin the programmed acquisition time selected by
bits b
1
and b
0
of the configuration register The SYNC pin
will go high indicating that a conversion sequence has be-
gun following the end of the acquisition period The RDY
and SYNC signal will fall low when the conversion is done
At this time new information such as a new acquisition time
and operational command can be written into the Configura-
tion register or it can remain unchanged With the START
command in the Configuration register a read from the
ADC12041 will place the entire 13-bit conversion result
stored in the data register on the data bus The rising edge
of the read pulse will immediately force the RDY output high
and begin the programmed acquisition time selected by bits
b
1 and b 0 of the configuration register The SYNC will then
go high at the end of the programmed acquisition time
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