Rainbow Electronics MAX5547 - Manual (Page 9)

Set CS low to begin clocking input data at DIN on the
falling edge of SCLK (see Figure 1). Serial communica-
tions to the shift register consist of a 16-bit command
word loaded from DIN. The first four control bits
(C3–C0) determine the target register (see Table 1).
The next 10 data bits set the current-sink level. D9 is
the MSB and D0 the LSB. Set bits S1 and S0 to zero for
proper operation. Data is latched into the appropriate
DAC register on the 16th SCLK falling edge. After writ-
ing 16 bits, drive CS high. Keep CS low throughout the
entire 16-bit word.
Write the command word to configure DAC registers A
and B individually or both registers at the same time.
The command word also determines whether the DACs
use the internal or external reference.
The MAX5547 powers up in external reference mode with
DAC registers A and B set to I
FS = 1.2mA at code 000h.
Applications Information
Power Sequencing
Ensure the voltages applied at REF, OUTA, and OUTB
do not exceed V
DD at any time. If proper power
sequencing is not possible, connect an external
Schottky diode between REF/OUTA/OUTB and V
DD to
ensure compliance with the absolute maximum ratings.
Power-Supply Bypassing and Ground
Management
Digital or AC transient signals on GND create noise at
the analog output. Return GND to the highest quality
ground plane available. For extremely noisy environ-
ments, bypass both REF and V
DD
to GND with 10µF
and 0.1µF capacitors in parallel, with the 0.1µF capaci-
tor as close to the device as possible. Careful PC
board ground layout minimizes crosstalk between the
DAC outputs and digital inputs.
MAX5547
Dual, 10-Bit, Current-Sink Output DAC
_______________________________________________________________________________________ 9
CS
SCLK
t CSS
t DS
t DH
t CL t CH
C3 C2 S1 S0
t
CP
t
CSH
t CSW
DIN
Figure 1. SPI Serial-Interface Timing Diagram