Table 2. dilvl and li output, Table 3. qlvl and rx output – Rainbow Electronics MAX14821 User Manual
Page 20
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MAX14821
IO-Link Device Transceiver
Table 2. DiLvl and LI Output
Table 3. QLvl and RX Output
V
DI
(V)
DiLvl BIT
LI OUTPUT
< 5.2
0
High
> 8
1
Low
V
C/Q
(V)
QLvl BIT
RX OUTPUT
< 8
1
High
>13
0
Low
BIT
NAME
DESCRIPTION
D4
QLvl
C/Q Logic Level. The QLvl bit is the inverse of the logic level at C/Q. QLvl is 1 when the
C/Q input level is low (< 8V) and is 0 when the C/Q logic level is high (> 13V) (Table 3).
QLvl remains active when the C/Q receiver is disabled (RxDis = 1). QLvl does not affect
IRQ. QLvl is not changed when the Status register is read.
D3
C/QFaultInt
C/Q Fault Interrupt. The C/QFaultInt interrupt bit and C/QFault bit (in the Mode register)
are set when a short circuit or voltage fault occurs on the C/Q driver output (see the C/Q
Fault Detection section for more information). IRQ asserts when C/QFault is 1. Read the
Status register to clear the C/QFaultInt bit and deassert IRQ.
D2
UV33Int
Internal 3.3V LDO (LDO33) Undervoltage Warning. Both the UV33Int interrupt bit and
the UV33En bit (in the Mode register) are set when V
LDO33
falls below the 2.4V LDO33
undervoltage threshold. If UV33En is set in the Mode register, IRQ asserts low when the
UV33Int bit is 1. Read the Status register to clear the UV33Int bit and deassert IRQ.
Set the UV33En bit to 1 in the Mode register to enable undervoltage monitoring for
UV33Int. When enabled, UV asserts high when the UV33Int bit is 1. UV deasserts when
V
LDO33
rises above the LDO33 undervoltage threshold.
D1
UV24Int
V
CC
Undervoltage Interrupt. The UV24Int interrupt bit and the UV24 bit (in the Mode
register) are set when the V
CC
voltage falls below the 7.4V undervoltage threshold. IRQ
asserts low when the UV24Int bit is 1. Read the Status register to clear the UV24Int bit
and deassert IRQ. V
CC
undervoltage detection cannot be disabled.
D0
OTempInt
Overtemperature Warning. The OTempInt interrupt bit and the OTemp bit (in the Mode
register) are set when a high-temperature condition is detected by the device. OTemp
is set when the temperature of the die exceeds +115
N
C (typ). OTempInt is set and IRQ
asserts when the OTemp bit is 1. The OTempInt bit is cleared and IRQ deasserts when
the Status register is read.
Once cleared, OTempInt is not reset if the die temperature remains above the thermal
warning threshold and does not fall below +95
°C.