Rainbow Electronics ADC08062 - Manual (Page 12)

Application Information
(Continued)
A conversion begins with the Voltage Estimator comparing
the analog input signal against the six tap voltages on the
estimator DAC The estimator decoder then selects one of
the groups of tap points along the MSB Ladder These eight
tap points are then connected to the eight flash compara-
tors For example if the analog input signal applied to V
IN
is
between 0 and of V REF (V REF e V REF a b V REF b
) the
estimator decoder instructs the comparator multiplexer to
select the eight tap points between 8 256 and 2 8 of V
REF
and connects them to the eight flash comparators The first
flash conversion is now performed producing the five MSBs
of data
The remaining three LSBs are generated next using the
same eight comparators that were used for the first flash
conversion As determined by the results of the MSB flash
a voltage from the MSB Ladder equivalent to the magnitude
of the five MSBs is subtracted from the analog input voltage
as the upper switch is moved from position one to position
two The resulting remainder voltage is applied to the eight
flash comparators and with the lower switch in position two
compared with the eight tap points from the LSB Ladder
By using the same eight comparators for both flash conver-
sions the number of comparators needed by the multi-step
converter is significantly reduced when compared to stan-
dard half-flash techniques
Voltage Estimator errors as large as of V REF (16 LSBs)
will be corrected since the flash comparators are connected
to ladder voltages that extend beyond the range specified
by the Voltage Estimator For example if
V
REF k V
IN k
V REF the Voltage Estimator’s comparators tied to the
tap points below V REF will output ‘‘1’’s (000111) This is
decoded by the estimator decoder to ‘‘10’’ The eight flash
comparators will be placed at the MSB Ladder tap points
between
V
REF
and V
REF
The overlap of V
REF
on
each side of the Voltage Estimator’s span will automatically
correct an error of up to 16 LSBs (16 LSBs e 312 5 mV for
V
REF e 5V) If the first flash conversion determines that the
input voltage is between V
REF
and 4 8 V
REF b LSB 2
the Voltage Estimator’s output code will be corrected by
subtracting ‘‘1’’ This results in a corrected value of ‘‘01’’ If
the first flash conversion determines that the input voltage is
between 8 16 V
REF b LSB 2 and V REF the Voltage
Estimator’s output code remains unchanged
After correction the 2-bit data from both the Voltage Esti-
mator and the first flash conversion are decoded to produce
the five MSBs Decoding is similar to that of a 5-bit flash
converter since there are 32 tap points on the MSB Ladder
However 31 comparators are not needed since the Voltage
Estimator places the eight comparators along the MSB Lad-
der where reference tap voltages are present that fall above
and below the magnitude of V
IN Comparators are not need-
ed outside this selected range If a comparator’s output is a
‘‘0’’ all comparators above it will also have outputs of ‘‘0’’
and if a comparator’s output is a ‘‘1’’ all comparators below
it will also have outputs of ‘‘1’’
2 0 DIGITAL INTERFACE
The ADC08061 2 has two basic interface modes which are
selected by connecting the MODE pin to a logic high or low
2 1 RD Mode
With a logic low applied to the MODE pin the converter is
set to Read mode In this configuration (see
Figure 1 ) a
complete version is done by pulling RD low and holding
low until the conversion is complete and output data ap-
pears This typically takes 655 ns The INT (interrupt) line
goes low at the end of conversion A typical delay of 50 ns is
needed between the rising edge of RD (after the end of a
conversion) and the start of the next conversion (by pulling
RD low) The RDY output goes low after the falling edge of
CS and goes high at the end-of-conversion It can be used
to signal a processor that the converter is busy or serve as a
system Transfer Acknowledge signal For the ADC08062
the data generated by the first conversion cycle after power-
up is from an unknown channel
2 2 RD Mode Pipelined Operation
Applications that require shorter RD pulse widths than those
used in the Read mode as described above can be
achieved by setting RD’s width between 200 ns – 400 ns
(Figure 4) RD pulse widths outside this range will create
conversion linearity errors These errors are caused by exer-
cising internal interface logic circuitry using CS and or RD
during a conversion
When RD goes low a conversion is initiated and the data
from the previous conversion is available on the DB0 – DB7
outputs Reading D0 – D7 for the first two times after power-
up produces random data The data will be valid during the
third RD pulse that occurs after the first conversion
2 3 WR-RD (WR then RD) Mode
The ADC08061 2 is in the WR-RD mode with the MODE
pin tied high A conversion starts on the falling edge of the
WR signal There are two options for reading the output
data which relate to interface timing If an interrupt-driven
scheme is desired the user can wait for the INT output to go
low before reading the conversion result (see
Figure 2b )
Typically INT will go low 520 ns maximum after WR’s ris-
ing edge However if a shorter conversion time is desired
the processor need not wait for INT and can exercise a read
after only 350 ns (see
Figure 2a ) If RD is pulled low before
INT goes low INT will immediately go low and data will ap-
pear at the outputs This is the fastest operating mode (t
RD
s t
INTL
) with a conversion time including data access time
of 560 ns Allowing 100 ns for reading the conversion data
and the delay between conversions gives a total throughput
time of 660 ns (throughput rate of 1 5 MHz)
2 4 WR-RD Mode with Reduced Interface
System Connection
CS and RD can be tied low using only WR to control the
start of conversion for applications that require reduced digi-
tal interface while operating in the WR-RD mode
(Figure 3)
Data will be valid approximately 705 ns following WR’s ris-
ing edge
2 5 Multiplexer Addressing
The ADC08062 has 2 multiplexer inputs These are selected
using the A0 multiplexer channel selection input Table I
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