Rainbow Electronics MAX7359 - Manual (Page 15)

MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
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MAX7359
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 4),
which the recipient uses to handshake receipt of each
byte of data. Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7359, the MAX7359
generates the acknowledge bit because the MAX7359
is the recipient. When the MAX7359 is transmitting to
the master, the master generates the acknowledge bit
because the master is the recipient.
Slave Addresses
The MAX7359 has a 7-bit long slave address (Figure
5). The bit following a 7-bit slave address is the R/
W bit,
which is low for a write command and high for a read
command.
The first 4 bits (MSBs) of the MAX7359 slave address
are always 0111. Slave address bits A3, A2, and A1
correspond, by the matrix in Table 10, to the states of
the device address input AD0, and A0 corresponds to
the R/
W bit. The AD0 input can be connected to any of
four signals: GND, V CC , SDA, or SCL, giving four possi-
ble slave address pairs, allowing up to four MAX7359
devices to share the bus. Because SDA and SCL are
dynamic signals, care must be taken to ensure that AD0
transitions no sooner than the signals on the SDA and
SCL pins.
The MAX7359 monitors the bus continuously, waiting for
a START condition followed by its slave address. When
the MAX7359 recognizes its slave address, it acknowl-
edges and is then ready for continued communication.
Bus Timeout
The MAX7359 features a 20ms minimum bus timeout on
the 2-wire serial interface, largely to prevent the
MAX7359 from holding the SDA I/O low during a read
transaction if the SCL hangs for any reason before a seri-
al transaction has been completed. Bus timeout oper-
ates by causing the MAX7359 to internally terminate a
serial transaction, either read or write, if SCL low
exceeds 20ms. After a bus timeout, the MAX7359 waits
for a valid START condition before responding to a con-
secutive transmission. This feature can be enabled or
disabled under user control by writing to the configura-
tion register (Table 4).
DEVICE ADDRESS
PIN ADO
A7 A6 A5 A4 A3 A2 A1 A0
GND 0 1 1 1 0 0 0 R/W
V
CC
0 1 1 1 0 1 0 R/W
SDA 0 1 1 1 1 0 0 R/W
SCL 0 1 1 1 1 1 1 R/W
Table 10. 2-Wire Interface Address Map
SDA
SCL
0 1 1 A3 A2 A1 1
MSB LSB
ACK R/W
Figure 5. Slave Address
SCL
SDA
BY
TRANSMITTER
CLOCK PULSE FOR
ACKNOWLEDGE
START
CONDITION
SDA
BY
RECEIVER
1 2 8 9
S
Figure 4. Acknowledge