Rainbow Electronics ADC10321 - Manual (Page 12)

Functional Description
The ADC10321 maintains excellent dynamic performance
for input signals up to half the clock frequency. The use of an
internal sample-and-hold amplifier (SHA) enables sustained
dynamic performance for signals of input frequency beyond
the clock rate, lowers the converter’s input capacitance and
reduces the number of external components required.
The analog signal at V
IN
that is within the voltage range set
by V
REF
+ S and V
REF
− S are digitized to ten bits at up to 25
MSPS. Input voltages below V
REF
− S will cause the output
word to consist of all zeroes. Input voltages above V
REF
+ S
will cause the output word to consist of all ones. V
REF
+ S has
a range of 2.3 to 4.0 Volts, while V
REF
− S has a range of 1.3
to 3.0 Volts. V
REF
+ S should always be at least 1.0 Volt more
positive than V
REF
− S.
Data is acquired at the falling edge of the clock and the
digital equivalent of that data is available at the digital out-
puts 2.0 clock cycles plus t
OD
later. The ADC10321 will
convert as long as the clock signal is present at pin 9 and the
PD pin is low. The Output Enable pin (OE), when low,
enables the output pins. The digital outputs are in the high
impedance state when the OE pin is low or the PD pin is
high.
Applications Information
1.0 THE ANALOG INPUT
The analog input of the ADC10321 is a switch (transmission
gate) followed by a switched capacitor amplifier. The capaci-
tance seen at the input changes with the clock level, appear-
ing as about 3pF when the clock is low, and about 5pF when
the clock is high. This small change in capacitance can be
reasonably assumed to be a fixed capacitance. Care should
be taken to avoid driving the input beyond the supply rails,
even momentarily, as during power-up.
The LMH6702 has been found to be a good device to drive
the ADC10321 because of its low voltage capability, wide
bandwidth, low distortion and minimal Differential Gain and
Differential Phase. The LMH6702 performs best with a feed-
back resistor of about 100 ohms.
Care should be taken to keep digital noise out of the analog
input circuitry to maintain highest noise performance.
2.0 REFERENCE INPUTS
Note: Throughout this data sheet reference is made to
V
REF
+ and to V
REF
−. These refer to the internal voltage
across the reference ladder and are, nominally, V
REF
+ S and
V
REF
− S, respectively.
Figure 4 shows a simple reference biasing scheme with
minimal components. While this circuit might suffice for
some applications, it does suffer from thermal drift because
the external resistor at pin 2 will have a different temperature
coefficient than the on-chip resistors. Also, the on-chip resis-
tors, while well matched to each other, will have a large
tolerance compared with any external resistors, causing the
value of V
REF
- to be quite variable. No d.c. current should be
allowed to flow through pin 1 or 32 or linearity errors will
result near the zero scale and full scale ends of the signal
excursion. The sense pins were designed to be used with
high impedance opamp inputs for high accuracy biasing.
The circuit of Figure 5 is an improvement over the circuit of
Figure 4 in that both ends of the reference ladder are defined
with reference voltages. This reduces problems of high ref-
erence variability and thermal drift, but requires two refer-
ence sources.
In addition to the usual reference inputs, the ADC10321 has
two sense outputs for precision control of the ladder volt-
ages. These sense outputs (V
REF
+ S and V
REF
− S) compen-
sate for errors due to IR drops between the source of the
reference voltages and the ends of the reference ladder
itself.
With the addition of two op-amps, the voltages at the top and
bottom of the reference ladder can be forced to the exact
value desired, as shown in Figure 6.
ADC10321
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