Rainbow Electronics DS2482-800 - Manual (Page 12)

DS2482-800: Eight-Channel 1-Wire Master
12 of 22
1-Wire Reset
Command Code B4h
Command Parameter None
Description
Generates a 1-Wire Reset/Presence Detect cycle (Figure 5) at the
selected IO channel. The state of the 1-Wire line is sampled at t
SI
and t
MSP
and the result is reported to the host processor through the status register,
bits PPD and SD.
Typical Use To initiate or end any 1-Wire communication sequence.
Restriction
1-Wire activity must have ended before the DS2482 can process this
command.
Error Response
Command code will not be acknowledged if 1WB = 1 at the time the
command code is received and the command will be ignored.
Command Duration
t
RSTL
+ t
RSTH
+ maximum 262.5ns, counted from the falling SCL edge of the
command code acknowledge bit.
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the command
code acknowledge bit.
Read Pointer Position Status Register (for busy polling)
Status Bits Affected
1WB (set to 1 for t
RSTL
+ t
RSTH
),
PPD is updated at t
RSTL
+ t
MSP
,
SD is updated at t
RSTL
+ t
SI
Configuration Bits Affected 1WS, PPM, APU apply
1-Wire Single Bit
Command Code 87h
Command Parameter Bit Byte
Description
Generates a single 1-Wire time slot with a bit value ‘V’ as specified by the
bit byte at the selected 1-Wire IO channel. A ‘V’ value of 0b will generate a
write-zero time slot (Figure 6), a value of 1b will generate a write one slot,
which also functions as a read data time slot (Figure 7). In either case the
logic level at the 1-Wire line is tested at t
MSR
and SBR is updated.
Typical Use
To perform single bit writes or reads on a 1-Wire IO channel when single
bit communication is necessary (the exception).
Restriction
1-Wire activity must have ended before the DS2482 can process this
command.
Error Response
Command code and bit byte will not be acknowledged if 1WB = 1 at the
time the command code is received and the command will be ignored.
Command Duration
t
SLOT
+ maximum 262.5ns, counted from the falling SCL edge of the first
bit (MS bit) of the bit byte.
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the MS bit of the
bit byte.
Read Pointer Position Status Register (for busy polling and data reading)
Status Bits Affected
1WB (set to 1 for t
SLOT
)
SBR is updated at t
MSR
DIR (may change its state)
Configuration Bits Affected 1WS, APU, SPU apply
Bit Allocation in the Bit Byte
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
V x x x x x x x
x = don’t care