Rainbow Electronics DS3131 - Manual (Page 39)

DS3131
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5.3 Status and Interrupt
5.3.1 General Description of Operation
There are two status registers in the device, status master (SM) and status for DMA (SDMA). Both
registers report events in real-time as they occur by setting a bit within the register to 1. Each bit has the
ability to generate an interrupt at the PCI bus through the PINTA output signal pin and if the local bus is
in the configuration mode, then an interrupt also be created at the LINT output signal pin. Each status
register has an associated interrupt mask register, which can allow/deny interrupts from being generated
on a bit-by-bit basis. All status remains active even if the associated interrupt is disabled.
SM Register
The status master (SM) register reports events that occur at the port interface, at the BERT receiver, at
the PCI bus and at the local bus. See
Figure 5-1 for details.
The BERT receiver reports three events: a change in the receive synchronizer status, a bit error being
detected, and if either the bit counter or the error counter overflows. Each of these events can be masked
within the BERT function through the BERT control register (BERTC0). If the software detects that the
BERT has reported an event, the software must read the BERT status register (BERTEC0) to determine
which event(s) has occurred.
The SM register also reports events as they occur in the PCI bus and the local bus. There are no control
bits to stop these events from being reported in the SM register. When the local bus is operated in the
PCI bridge mode, SM reports any interrupts detected through the local bus LINT input signal pin and if
any timing errors occur because the external timing signal LRDY. When the local bus is operated in the
configuration mode, the LBINT and LBE bits are meaningless and should be ignored.
SDMA Register
The status DMA (SDMA) register reports events pertaining to the receive and transmit DMA blocks as
well as the receive HDLC controller and FIFO. The SDMA reports when the DMA reads from either the
receive free queue or transmit pending queue or writes to the receive or transmit done queues. Also
reported are error conditions that might occur in the access of one of these queues. The SDMA reports if
any of the HDLC channels experiences an FIFO overflow/underflow condition and if the receive HDLC
controller encounters a CRC error, abort signal, or octet length problem on any of the HDLC channels.
The host can determine which specific HDLC channel incurred an FIFO overflow/underflow, CRC error,
octet length error, or abort by reading the status bits as reported in done queues, which are created by the
DMA. There are no control bits to stop these events from being reported in the SDMA register.