Rainbow Electronics ATF1504ASVL - Manual (Page 8)

8
ATF1504ASV(L)
1409H–PLD–09/02
Input Diagram
I/O Diagram
Speed/Power
Management
The ATF1504ASV(L) has several built-in speed and power management features. The
ATF1504ASV(L) contains circuitry that automatically puts the device into a low power
standby mode when no logic transitions are occurring. This not only reduces power con-
sumption during inactive periods, but also provides proportional power savings for most
applications running at system speeds below 5 MHz. This feature may be selected as a
device option.
To further reduce power, each ATF1504ASV(L) macrocell has a reduced-power bit fea-
ture. This feature allows individual macrocells to be configured for maximum power
savings. This feature may be selected as a design option.
All ATF1504ASV(L) also have an optional power-down mode. In this mode, current
drops to below 5 mA. When the power-down option is selected, either PD1 or PD2 pins
(or both) can be used to power down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down fea-
ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals.