Rainbow Electronics ATF1500ABV - Manual (Page 5)

5
ATF1500ABV
0723I–08/01
ATF1500ABV Macrocell
ATF1500ABV
Macrocell
The ATF1500ABV macrocell is flexible enough to support highly complex logic functions oper-
ating at high speed. The macrocell consists of five sections: product terms and product term
select multiplexer; OR/XOR/CASCADE logic; a flip-flop; output select and enable; and logic
array inputs.
Product Terms
and Select Mux Each ATF1500ABV macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to
the macrocell logic gates and control signals. The PTMUX programming is determined by the
design compiler, which selects the optimum macrocell configuration.
OR/XOR/
CASCADE Logic The ATF1500ABV macrocell’s OR/XOR/CASCADE logic structure is designed to efficiently
support all types of logic. Within a single macrocell, all the product terms can be routed to the
OR gate, creating a five-input AND/OR sum term. With the addition of the CASIN from neigh-
boring macrocells, this can be expanded to as many as 40 product terms with little small
additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high or low level. For combinatorial outputs, the fixed-level input allows
output polarity selection. For registered functions, the fixed levels allow De Morgan minimiza-
tion of the product terms. The XOR gate is also used to emulate JK-type flip-flops.