Rainbow Electronics ADC10D040 - Manual (Page 27)

Applications Information
(Continued)
7.0 DYNAMIC PERFORMANCE
The ADC10D040 is a.c. tested and its dynamic performance
is guaranteed. To meet the published specifications, the
clock source driving the CLK input must be free of jitter. For
best dynamic performance, isolating the ADC clock from any
digital circuitry should be done with adequate buffers, as with
a clock tree. See Figure 9.
8.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, no input should go more
than 300 mV beyond the supply pins, Exceeding these limits
on even a transient basis can cause faulty or erratic opera-
tion. It is not uncommon for high speed digital circuits (e.g.,
74F and 74AC devices) to exhibit overshoot and undershoot
that goes a few hundred millivolts beyond the supply rails. A
resistor of 50
Ω to 100Ω in series with the offending digital
input, close to the source, will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC10D040 (or any device) with a device that is powered
from supplies outside the range of the ADC10D040 supply.
Such practice may lead to conversion inaccuracies and even
to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers have to charge for
each conversion, the more instantaneous digital current is
required from V
DR
and DR GND. These large charging cur-
rent spikes can couple into the analog section, degrading
dynamic performance. Adequate bypassing and attention to
board layout will reduce this problem. Buffering the digital
data outputs (with a 74ACTQ841, for example) may be
necessary if the data bus to be driven is heavily loaded.
Dynamic performance can also be improved by adding se-
ries resistors of 47
Ω to 56Ω at each digital output, close to
the ADC output pins.
Using a clock source with excessive jitter. This will cause
the sampling interval to vary, causing excessive output noise
and a reduction in SNR and SINAD performance. The use of
simple gates with RC timing as a clock source is generally
inadequate.
Using the same voltage source for V
D
and external digi-
tal logic. As mentioned in Section 5.0, V
D
should use the
same power source used by V
A
and other analog compo-
nents, but should be decoupled from V
A
.
20029775
FIGURE 8. An Acceptable Layout Pattern
20029776
FIGURE 9. Isolating the ADC Clock from Digital
Circuitry
ADC10D040
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