Rainbow Electronics DS1087L - Manual (Page 9)

DS1087L
3.3V Spread-Spectrum EconOscillator
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Bits 3 to 0: Prescaler Divider. The prescaler bits
(bits P3 to P0) divide the master oscillator
frequency by 2
x where x can be from 0 to
8. Any prescaler bit value entered that is
greater than 8 decodes as 8.
ADDR Register
Bit 3: Write Control. The WC bit determines if
the EEPROM is to be written to after reg-
ister contents have been changed. If WC
= 0 (default), EEPROM is written automat-
ically after a write. If WC = 1, the EEP-
ROM is only written when the WRITE EE
command is issued. See the WRITE EE
Command section for more information.
Bits 2 to 0: Address. The A0, A1, A2 bits determine
the lower nibble of the 2-wire slave
address.
WRITE EE Command
The WRITE EE command is useful in closed-loop appli-
cations where the registers are frequently written. In
applications where the register contents are frequently
written, the WC bit should be set to 1 to prevent wear-
ing out the EEPROM. Regardless of the value of the WC
bit, the value of the ADDR register is always written
immediately to EEPROM. When the WRITE EE com-
mand has been received, the contents of the registers
are copied into the EEPROM, thus locking in the regis-
ter settings.
_______2-Wire Serial Port Operation
2-Wire Serial Data Bus
The DS1087L communicates through a 2-wire serial
interface. A device that sends data onto the bus is
defined as a transmitter, and a device receiving data
as a receiver. The device that controls the message is
called a "master." The devices that are controlled by the
master are "slaves." A master device that generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions must control the
bus. The DS1087L operates as a slave on the 2-wire
bus. Connections to the bus are made through the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see
Figures 3 and 5):
• Data transfer can be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH are
interpreted as control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
HIGH.
Start data transfer: A change in the state of the
data line, from HIGH to LOW, while the clock is
HIGH, defines a START condition.
Stop data transfer: A change in the state of the
data line, from LOW to HIGH, while the clock line
is HIGH, defines the STOP condition.
STOP
CONDITION
OR REPEATED
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
ACK
START
CONDITION
ACK
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SLAVE ADDRESS
MSB
SCL
SDA
R/W
DIRECTION
BIT
1 2 6 7 8 9 1 2 8 9 3–7
Figure 3. 2-Wire Data Transfer Protocol