Rainbow Electronics DS4026 - Manual (Page 11)

• During data transfer, the data line must remain stable
whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as
control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
high.
Start data transfer: A change in the state of the data
line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the state of the data
line from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The state of the data line represents valid
data when, after a START condition, the data line is
stable for the duration of the high period of the clock
signal. The data on the line must be changed during
the low period of the clock signal. There is one clock
pulse per bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between the START and the
STOP conditions is not limited, and is determined by
the master device. The information is transferred
byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
(ACK) after the reception of each byte. The master
device must generate an extra clock pulse that is
associated with this acknowledge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
Figures 4 and 5 detail how data transfer is accom-
plished on the I
2 C bus. Depending upon the state of
the R/ W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge (ACK) bit
after each received byte.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last
received byte, a not acknowledge (NACK) is
returned.
The master device generates all the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a repeat-
ed START condition. Because a repeated START
condition is also the beginning of the next serial
transfer, the bus is not released.
DS4026
10MHz to 51.84MHz TCXO
____________________________________________________________________ 11
A XXXXXXXX A 1000001 S 0 XXXXXXXX A XXXXXXXX A XXXXXXXX A P
<SLAVE
ADDRESS>
S = START
A = ACKNOWLEDGE
P = STOP
R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 82h
<RW>
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
<DATA (n + X)> <DATA (n + 1)> <DATA (n)>
<WORD
ADDRESS (n)>
Figure 4. Slave Receiver Mode (Write Mode)
A XXXXXXXX A 1000001 S 1 XXXXXXXX A XXXXXXXX A XXXXXXXX A P
<SLAVE
ADDRESS>
S = START
A = ACKNOWLEDGE
P = STOP
A = NOT ACKNOWLEDGE
R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 83h
<RW>
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY
A NOT ACKNOWLEDGE (A) SIGNAL
<DATA (n + X)> <DATA (n + 2)> <DATA (n + 1)> <DATA (n)>
Figure 5. Slave Transmitter Mode (Read Mode)