Rainbow Electronics DS2756 - Manual (Page 25)

DS2756: High-Accuracy Battery Fuel Gauge with Programmable Suspend Mode
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I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols or signaling types
used are:
1) Initialization sequence (Reset Pulse followed by Presence Pulse)
2) Write 0
3) Write 1
4) Read Data
All signaling is initiated by the bus master. Except for the Presence Pulse, all falling edges are created by the bus
master. The initialization sequence required to begin communication with the DS2756 is shown in Figure 22. A
presence pulse following a reset pulse indicates the DS2756 is ready to accept a net address command. The bus
master transmits (Tx) a reset pulse for t
RSTL
. The bus master then releases the line and goes into receive mode
(Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the rising edge on the DQ pin,
the DS2756 waits for t
PDH
and then transmits the Presence Pulse for t
PDL
.
Figure 22. 1-Wire Initialization Sequence
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level to a logic-low
level. There are two types of write-time slots: write 1 and write 0. All write-time slots must be t
SLOT
in duration with a
1 ms minimum recovery time, t
REC
, between cycles.
The bus master generates a write 1 time slot by pulling 1-Wire bus line low for t
LOW1
and then releasing it. The bus
must be pulled high within 15 ms in Standard mode or 2ms in Overdrive mode after the start of the write-time slot.
The bus master generates a write 0 time slot by pulling 1-Wire bus line low and then holding it low for t
LOW0
, or up to
the end of the write-time slot.
The DS2756 samples the 1-Wire bus after the line falls, sampling occurs between 15
ms and 60ms in Standard
mode and between 2 ms and 6ms in Overdrive mode. If the line is high when sampled by the DS2756, a write 1
occurs, that is, the DS2756 accepts the bit value to be a 1. If the line is low when sampled, a write 0 occurs, that is,
the DS2756 accepts the bit value to be a 0. See Figure 23 for more information.
READ-TIME SLOTS
A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a logic-low level.
The bus master generated read-time slot results in a read 1 and read 0 depending on the data presented by the
DS2756. All read-time slots must be t
SLOT
in duration with a 1 ms minimum recovery time, t
REC
, between cycles.
The bus master initiates a read-time slot by pulling the bus line low for at least 1 ms and then releasing it to allow the
DS2756 to present valid data. The DS2756 generates a read 0 by holding the line low. The line is held low for at
least the Read Data Valid time (t
RDV
) from the start of the read-time slot. The DS2756 releases the bus line and
allows it to be pulled high by the external pullup resistor some time after t
RDV
but before the end of the read-time
slot. A read 1 is generated by not holding the line low after the time slot is initiated by the master. The line is
allowing it to be pulled high as soon as it is released by the master. The bus master must sample the bus after
initializing the time slot and before t
RDV
to read the data value transmitted by the DS2756. Sampling should occur
as close to t
RDV
as possible to allow for the rise time of the passive pullup 1-Wire bus. See Figure 23 for more
information.
PACK
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW DS2756 ACTIVE LOW
RESISTOR PULLUP BOTH BUS MASTER AND
DS2756 ACTIVE LOW
t
RSTL
t
PDL
t
RSTH
t
PDH
PACK
DQ