Rainbow Electronics ADC10D020 - Manual (Page 23)

Typical Performance Characteristics
V
A
= V
D
= V
DR
= 3.0V, f
CLK
= 20 MHz, unless otherwise
specified (Continued)
Spectral Response @ f
IN
= 99 MHz IMD Response @ f
IN
= 4.9 MHz, 5.1 MHz
20025581 20025568
Functional Description
Using a subranging architecture, the ADC10D020 achieves
9.5 effective bits over the entire Nyquist band at 20 MSPS
while consuming just 150 mW. The use of an internal
sample-and-hold amplifier (SHA) not only enables this sus-
tained dynamic performance, but also lowers the converter’s
input capacitance and reduces the number of external com-
ponents required.
Analog signals at the “I” and “Q” inputs that are within the
voltage range set by V
REF
and the GAIN pin are digitized to
ten bits at up to 30 MSPS. V
REF
has a range of 0.8V to 1.5V,
providing a differential peak-to-peak input range of 0.8 V
P-P
to 1.5 V
P-P
with the GAIN pin at a logic low, or an input range
of 1.6 V
P-P
to 3.0 V
P-P
with the GAIN pin at a logic high.
Differential input voltages less than −V
REF
/2 with the GAIN
pin low, or less than −V
REF
with the GAIN pin high will cause
the output word to indicate a negative full scale. Differential
input voltages greater than V
REF
/2 with the GAIN pin low, or
greater than V
REF
with the GAIN pin high, will cause the
output word to indicate a positive full scale.
Both “I” and “Q” channels are sampled simultaneously on the
falling edge of the clock input, while the timing of the data
output depends upon the mode of operation.
In the parallel mode, the “I” and “Q” output busses contain
the conversion result for their respective inputs. The “I” and
“Q” channel data are present and valid at the data output
pins t
OD
after the rising edge of the input clock. In the
multiplexed mode, “I” channel data is available at the digital
outputs t
OD
after the rise of the clock edge, while the “Q”
channel data is available at the digital outputs t
OD
after the
fall of the clock. However, a delayed I/Q output signal should
be used to latch the output for best, most consistent results.
Data latency in the parallel mode is 2.5 clock cycles. In the
multiplexed mode data latency is 2.5 clock cycles for the “I”
channel and 3.0 clock cycles for the “Q” channel. The
ADC10D020 will convert as long as the clock signal is
present and the PD and STBY pins are low.
Throughout this discussion,V
CM
refers to the Common Mode
input voltage of the ADC10D020 while V
CMO
refers to its
Common Mode output voltage.
Applications Information
1.0 THE ANALOG SIGNAL INPUTS
Each of the analog inputs of the ADC10D020 consists of a
switch (transmission gate) followed by a switched capacitor
amplifier. The capacitance seen at each input pin changes
with the clock level, appearing as about 3 pF when the clock
is low, and about 6 pF when the clock is high. A switched
capacitance is harder to drive than is a larger, fixed capaci-
tance.
The CLC409 and the CLC428 dual op amp have been found
to be a good amplifiers to drive the ADC10D020 because of
their wide bandwidth and low distortion. They also have
good Differential Gain and Differential Phase performance.
Care should be taken to avoid driving the inputs beyond the
supply rails, even momentarily, as during power-up.
The ADC10D020 is designed for differential input signals for
best performance. With a 1.0V reference and the GAIN pin
at a logic low, differential input signals up to 1.0 V
P-P
are
digitized. See Figure 2. For differential signals, the input
common mode is expected to be about 1.5V, but the inputs
are not sensitive to the common-mode voltage and can be
anywhere within the supply rails (ground to V
A
) with little or
no performance degradation, as long as the signal swing at
the individual input pins is no more than 300 mV beyond the
supply rails. For single ended drive, operate the ADC10D020
with the GAIN pin at a logic low, connect one pin of the input
pair to 1.5V (V
CM
) and drive the other pin of the input pair
with 1.0 V
P-P
centered around 1.5V.
Because of the larger signal swing at one input for
single-ended operation, distortion performance will not be as
good as with a differential input signal. Alternatively,
single-ended to differential conversion with a transformer
provides a quick, easy solution for those applications not
requiring response to dc and low frequencies. See
Figure 3.
The 36
Ω
resistors and 110 pF capacitor values are chosen
to provide a cutoff frequency near the clock frequency to
compensate for the effects of input sampling. A lower time
constant should be used for undersampling applications.
ADC10D020
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