Rainbow Electronics DS3134 - Manual (Page 136)

DS3134
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010 = middle buffer transmission complete of a multi-buffer packet (DQS = 1)
011 = last buffer transmission complete of a multi-buffer packet (DQS = 1)
100 = software provisioning error; this channel was not enabled
101 = descriptor error; either byte count = 0 or channel code inconsistent with Pending Queue
110 = PCI error
111 = transmit FIFO error; it has underflowed
dword 0; Bits 29 to 31 / Unused. Not used by the DMA. Could be any value when read.
The Host will read from the Transmit Done Queue to find which data buffers and their associated
descriptors have completed transmission. The Transmit Done Queue is circular queue. To keep track of
the addresses of the circular queue in the Transmit Done Queue, there are a set of internal addresses
within the device that accessed by both the Host and the DMA. On initialization, the Host will configure
all of the registers shown in Table 8.2.4A. After initialization, the DMA will only write to (i.e. change)
the write pointer and the Host will only write to the read pointer.
Empty Case
The Transmit Done Queue is considered empty when the read and write pointers are identical.
Transmit Done Queue Empty State
empty descriptor
empty descriptor
empty descriptor
read pointer > empty descriptor < write pointer
empty descriptor
empty descriptor
empty descriptor
Full Case
The Transmit Done Queue is considered full when the read pointer is ahead of the write pointer by one
descriptor. Hence, one descriptor must always remain empty.
Transmit Done Queue Full State
valid descriptor
valid descriptor
empty descriptor < write pointer
read pointer > valid descriptor
valid descriptor
valid descriptor
valid descriptor