Rainbow Electronics DS1680 - Manual (Page 5)

DS1680
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3-WIRE SERIAL INTERFACE
Communication with the RTC and watchdog is accomplished through a simple 3-wire interface
consisting of the chip select (CS), serial clock (SCLK), and input/output (I/O) pins.
All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS
turns on the control logic, which allows access to the shift register for the address/command sequence.
Second, the CS signal provides a method of terminating either single byte or multip le byte (burst) data
transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data must
be valid during the clock’s rising edge and data bits are output on the clock’s falling edge. If the CS input
goes low, all data transfer terminates and the I/O pin goes to a high- impedance state.
Address and data bytes are always shifted LSB first into the I/O pin. Any transaction requires the
address/command byte to specify a read or write to a specific register followed by one or more bytes of
data. The address byte is always the first byte entered after CS is driven high. The most significant bit
(
RD /WR) of this byte determines if a read or write will take place. If this bit is 0, one or more read cycles
will occur. If this bit is 1, one or more write cycles will occur.
Data transfers can occur one byte at a time or in multiple-byte burst mode. After CS is driven high an
address is written to the DS1680. After the address, one or more data bytes can be read or written. For a
single byte transfer one byte is read or written and then CS is driven low. Multiple bytes can be read or
written to the DS1680 after the address has been written. Each read or write cycle causes the register
address to automatically increment. Incrementing continues until the device is disabled. After accessing
register 0Dh, the address wraps to 00h.
Data transfer for single-byte transfer and multiple-byte burst transfer is illustrated in Figures 2 and 3.
SINGLE-BYTE DATA TRANSFER Figure 2
MULTIPLE-BYTE BURST TRANSFER Figure 3