Rainbow Electronics HT93LC46 - Manual (Page 6)

ERASE
The ERASE instruction erases data at the
specified addresses in the programming enable
mode. After the ERASE op-code and the speci-
fied address have been issued, the data erase is
activated by the falling edge of CS. Since the
internal auto-timing generator provides all tim-
ing signals for the internal erase, so the SK
clock is not required. During the internal erase,
we can verify the busy/ready status if CS is
high. The DO pin will remain low but when the
operation is over, the DO pin will return to high
and further instructions can be executed.
WRITE
The WRITE instruction writes data into the
device at the specified addresses in the pro-
gramming enable mode. After the WRITE op-
code and the specified address and data have
been issued, the data writing is activated by the
falling edge of CS. Since the internal auto-tim-
ing generator provides all timing signal for the
internal writing, so the SK clock is not required.
The auto-timing write cycle includes an auto-
matic erase-before-write capability. So, it is not
necessary to erase data before the WRITE in-
struction. During the internal writing, we can
verify the busy/ready status if CS is high. The
DO pin will remain low but when the operation
is over, the DO pin will return to high and
further instructions can be executed.
ERAL
The ERAL instruction erases the entire 64 × 16
or 128 × 8 memory cells to logical “1” state in the
programming enable mode. After the erase-all
instruction set has been issued, the data erase
feature is activated by the falling edge of CS.
Since the internal auto-timing generator pro-
vides all timing signal for the erase-all opera-
tion, so the SK clock is not required. During the
internal erase-all operation, we can verify the
busy/ready status if CS is high. The DO pin will
remain low but when the operation is over, the
DO pin will return to high and further instruc-
tion can be executed.
WRAL
The WRAL instruction writes data into the en-
tire 64
× 16 or 128 × 8 memory cells in the pro-
gramming enable mode. After the write-all
instruction set has been issued, the data writ-
ing is activated by the falling edge of CS. Since
the internal auto-timing generator provides all
timing signals for the write-all operation, so the
SK clock is not required. During the internal
write-all operation, we can verify the
busy/ready status if CS is high. The DO pin will
remain low but when the operation is over the
DO pin will return to high and further instruc-
tion can be executed.
HT93LC46
6 6th May ’99