Rainbow Electronics BR24L01AFVM-W - Manual (Page 4)

BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
Memory ICs BR24L01AFV-W / BR24L01AFVM-W
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zBlock diagram
1 A0
A1 2
A2 3
GND 4
V CC 8
WP 7
6 SCL
SDA 5
1kbit EEPROM array
Control logic
High voltage generator Vcc level detect
7bit 8bit
ACK
STOP START
Address
decoder Slave word
address register
7bits
Data
register
Fig.2 BLOCK DIAGRAM
zPin configuration
BR24L01A-W
BR24L01AF-W
BR24L01AFJ-W
BR24L01AFV-W
BR24L01AFVM-W
V CC
A0
WP
A1
SCL
A2
SDA
GND
1 2 3 4
5 6 7 8
Fig.3 PIN LAYOUT
zPin name
Write protect input
Power supply
Function
Ground (0V)
Slave address set
Serial clock input
SDA
V CC
A0, A1, A2
Pin name
GND
WP
SCL
I / O
−
−
IN
IN
IN
IN / OUT
Slave and word address,
serial data input, serial data output
∗ 1 An open drain output requires a pull-up resistor.
∗ 1