Rainbow Electronics DS1315 - Manual (Page 3)

DS1315
041697 3/22
Communication with the Time Chip is established by
pattern recognition of a serial bit stream of 64 bits which
must be matched by executing 64 consecutive write
cycles containing the proper data on data in (D). All
accesses which occur prior to recognition of the 64–bit
pattern are directed to memory via the chip enable out-
put pin (CEO).
After recognition is established, the next 64 read or write
cycles either extract or update data in the Time Chip and
CEO remains high during this time, disabling the con-
nected memory.
Data transfer to and from the timekeeping function is
accomplished with a serial bit stream under control of
chip enable input (CEI), output enable (OE), and write
enable (WE). Initially, a read cycle using the CEI and OE
control of the Time Chip starts the pattern recognition
sequence by moving pointer to the first bit of the 64–bit
comparison register. Next, 64 consecutive write cycles
are executed using the CEI and WE control of the Time
Chip. These 64 write cycles are used only to gain
access to the Time Chip.
When the first write cycle is executed, it is compared to
bit 1 of the 64–bit comparison register. If a match is
found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a
match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle oc-
curs at any time during pattern recognition, the present
sequence is aborted and the comparison register point-
er is reset. Pattern recognition continues for a total of 64
write cycles as described above until all the bits in the
comparison register have been matched. (This bit pat-
tern is shown in Figure 2). With a correct match for
64 bits, the Time Chip is enabled and data transfer to or
from the timekeeping registers may proceed. The next
64 cycles will cause the Time Chip to either receive data
on D, or transmit data on Q, depending on the level of
OE pin or the WE pin. Cycles to other locations outside
the memory block can be interleaved with CEI cycles
without interrupting the pattern recognition sequence or
data transfer sequence to the Time Chip.
A standard 32,768 KHz quartz crystal can be directly
connected to the DS1315 via pins 1 and 2 (X1, X2). The
crystal selected for use should have a specified load ca-
pacitance (C
L
) of 6 pF. For more information on crystal
selection and crystal layout considerations, please con-
sult Application Note 58, “Crystal Considerations with
Dallas Real Time Clocks”.