Typical operating circuit description, Operation – Rainbow Electronics DS1216 User Manual

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DS1216

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TYPICAL OPERATING CIRCUIT

DESCRIPTION

The DS1216 SmartWatch RAM and SmartWatch ROM Sockets are 600mil-wide DIP sockets with a
built-in CMOS watch function, an NV RAM controller circuit, and an embedded lithium energy source.
The sockets provide an NV RAM solution for memory sized from 2k x 8 to 512k x 8 with package sizes
from 26 pins to 32 pins. When a socket is mated with a CMOS SRAM, it provides a complete solution to
problems associated with memory volatility and uses a common energy source to maintain time and date.
The SmartWatch ROM sockets use the embedded lithium source to maintain the time and date only. A
key feature of the SmartWatch is that the watch function remains transparent to the RAM. The
SmartWatch monitors V

CC

for an out-of-tolerance condition. When such a condition occurs, an internal

lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent loss of watch and RAM data.

Using the SmartWatch saves PC board space since the combination of SmartWatch and the mated RAM
take up no more area than the memory alone. The SmartWatch uses the V

CC

, data I/O 0,

CE

,

OE

, and WE

for RAM and watch control. All other pins are passed straight through to the socket receptacle.

The SmartWatch provides timekeeping information including hundredths of seconds, seconds, minutes,
hours, days, date, months, and years. The date at the end of the month is automatically adjusted for
months with fewer than 31 days, including correction for leap years. The SmartWatch operates in either
24-hour or 12-hour format with an AM/PM indicator.

OPERATION

Communication with the SmartWatch RAM is established by pattern recognition on a serial bit stream of
64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. On the SmartWatch ROM, communication with the clock is established using A2 and A0, and
either OE or CE. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.

V

CC

WE

OE

CE

1

2
3
4
5

6

7

8
9

[A2] 10

11

[A0] 12

13
14
15
16

32
31

29
28
27
26
25

24

23
22
21
20
19
18
17

GND

DQ0

RST

DS1216D/E/F/H

32-Pin Intelligent Socket

30

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