Ebi: external bus interface, Aic: advanced interrupt controller, Pio: parallel i/o controller – Rainbow Electronics AT75C320 User Manual
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AT75C320
1769A–07/01
EBI: External Bus
Interface
The EBI generates the signals that control access to external memory or memory-mapped
peripherals. The EBI is fully programmable and can address up to 64M bytes. The interface to
external devices is composed of common address and data buses and separate control lines
to allow the connection of static or dynamic devices.
The main features are:
•
External memory mapping
•
Up to four chip select lines
•
32- or 16-bit data bus
•
Byte write or byte select lines
•
Remap of boot memory
•
Support for both static and dynamic memories
•
Two different read protocols for static memories
•
Support for early read/early write for dynamic memories
•
Programmable wait state generation
•
Programmable data float time
AIC: Advanced
Interrupt
Controller
The AT75C320 has an 8-level priority interrupt controller. The interrupt controller outputs are
connected to the NFIQ (fast interrupt request) and the NIRQ (normal interrupt request) of the
ARM7TDMI core. The processor’s NFIQ can only be asserted by the external fast interrupt
request input (FIQ). The NIRQ line can be asserted by the interrupts generated by the on-chip
peripherals or by the external interrupt request line IRQ0.
An 8-level priority encoder allows the application to define the priority between the different
interrupt sources. Interrupt sources are programmed to be level sensitive or edge sensitive.
External sources can be programmed to be positive- or negative-edge triggered, or low- or
high-level sensitive.
PIO: Parallel I/O
Controller
The AT75C320 has 24 programmable I/O lines. They can all be programmed as inputs or out-
puts. To optimize the use of available package pins, most of them are multiplexed with
external signals of on-chip peripherals.
The PIO lines are controlled by two separate and identical PIO controllers called PIOA and
PIOB.
The PIO controllers enable the generation of an interrupt on input change and insertion of a
simple glitch filter on each PIO line.
Some I/O lines have enough drive capability to power a LED.