Rainbow Electronics DS1852 - Manual (Page 22)

DS1852
22 of 25
NOTES
1) All voltages are referenced to ground.
2) This is the time for one comparison. The complete cycle is this value multiplied by 3.
3) Absolute voltage error for B
in
, P
in
, and R
in
are valid from 0% to 98%.
4) ASEL = GND, SDA = SCL = D
in
= F
in
= L
in
= RS
in
= V
CC
.
5) The time to begin monitoring operations after V
CC
has risen above the analog minimum voltage.
6) After STOP command has been received. No acknowledges will be issued during this interval.
7) A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
> 250ns must
then be met. This will automatically be the case if the device does not stretch the low period of the
SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next
data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
8) After this period, the first clock pulse is generated.
9) The maximum t
HD:DAT
has only to be met if the device does not stretch the low period (t
LOW
) of the
SCL signal.
10) A device must internally provide a hold time of at least 300ns for the SDA signal (see the V
IH MIN
of
the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
11) C
B
— total capacitance of one bus line in picofarads, timing referenced to 0.9V
CC
and 0.1V
CC
.
12) Input levels equal either V
CC
or GND.