Rainbow Electronics DS2181A - Manual (Page 25)

DS2181A
041995 25/32
NOTES FOR FIGURES 23 THROUGH 27:
1. CAS multiframe alignment word received in error; RFER will transition high at first error occurrence and re-
main high as shown.
2. Previous CRC4 sub-multiframe 2 errored.
3. Frame alignment word errored.
4. Previous CRC4 sub-multiframe 1 errored.
RESET
A high-low transition on RST clears all internal registers
except the three error counters; a resync is initiated until
RST returns high. RST must be held low on system
power-up and when switching to/from the hardware
mode. Following reset, the host processor should up-
date all on-chip registers to establish desired operating
modes.
HARDWARE MODE
An on-chip hardware control mode simplifies prelimi-
nary system prototyping and serves applications which
do not require the features of the serial port. Tying SPS
low disables the serial port, clears all internal register lo-
cations except those shown below, and redefines pins
14 through 18 as mode control inputs. The mode control
inputs establish device operational characteristics as
shown in Table 8. The hardware mode simplifies device
retrofit into existing applications where control inter-
faces are designed with discrete logic.
HARDWARE MODE CONTROL Table 8
PIN NUMBER REGISTER LOCATION NAME AND DESCRIPTION
14
(16)
TINR.5 TRA - Transmit Remote Alarm
0 = Normal operation
1 = Enable alarm
15
(17)
TXR.2 TDMA - Transmit Distant Multiframe Alarm
0 = Normal operation
1 = Enable alarm
16
(18)
CCR.5/CCR.4 Data Format
0 = Input and output data AMI coded
1 = Input and output data HDB3 coded
17
(19)
CCR.3/CCR.2 Transmit and Receive CRC4 Multiframe
0 = Disabled
1 = Enabled
18
(20)
TCR.5/RCR.5 Transmit and Receive CAS Multiframe
0 = Enabled
1 = Disabled
NOTE:
1. Pin numbers for PLCC package are listed in parenthesis.