Rainbow Electronics ATF20V8CQZ - Manual (Page 4)

4
ATF20V8C Family
0408H–04/01
Functional Logic Diagram Description
The logic option and functional diagrams describe the
ATF20V8C architecture. Eight configurable macrocells can
be configured as a registered output, combinatorial I/O,
combinatorial output or dedicated input.
The ATF20V8C’s macrocell can be configured in one of
three different modes. Each mode makes the ATF20V8Cs
look like a different device. The ATF20V8Cs can be a reg-
istered output, combinatorial I/O, combinatorial output or
dedicated input. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The deter-
mining factors would be the usage of register versus
combinatorial outputs and dedicated outputs versus output
with output enable control.
The ATF20V8Cs have a user-controlled power-down pin,
which, when active, allows the user to place the device into
a “zero” standby power-down mode. The device can also
operate at high speed. Maximum pin-to-pin delays of 5 ns
are offered. Static power loss due to pull-up resistors is
eliminated by using input and output pin “keeper” circuits
that hold pins to their previous logic levels when idle.
The universal architecture of the ATF20V8Cs can be pro-
grammed to emulate many 24-pin PAL devices. The user
can download the subset device JEDEC programming file
to the PLD programmer and the ATF20V8Cs can be config-
ured to act like the chosen device.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
when programmed, protects the contents the ATF20V8Cs.
Eight bytes (64 fuses) of User Signature are accessible to
the user for purposes such as storing project name, part
number, revision or date. The User Signature is accessible
regardless of the state of the security fuse.
Note: 1. Only applicable for version 3.4 or lower.
Compiler Mode Selection
Registered Complex Simple Auto Select
ABEL, Atmel-ABEL P20V8R P20V8C P20V8 P20V8
CUPL G20V8MS G20V8MA G20V8 G20V8A
LOG/iC GAL20V8_R (1) GAL20V8_C7 (1) GAL20V8_C8 (1) GAL20V8
OrCAD-PLD “Registered” “Complex” “Simple” GAL20V8
PLDesigner P20V8 P20V8 P20V8 P20V8
Tango-PLD G20V8 G20V8 G20V8 G20V8