Rainbow Electronics DS3904 - Manual (Page 8)

DS3904
DS3904 Triple 128-Position Nonvolatile
Variable Digital Resistor/Switch
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Standby Mode
The DS3904 features a low-power mode that is auto-
matically enabled after power-on, after a stop com-
mand, and after the completion of all internal
operations.
Bus Reset
After any interruption in protocol, power loss, or system
reset, the following steps reset the DS3904:
1) Clock up to nine cycles.
2) Look for SDA high in each cycle while SCL is high.
3) Create a start condition while SDA is high.
Device Addressing
The DS3904 must receive an 8-bit device address byte
following a start condition to enable a specific device
for a read or write operation. The address byte is
clocked into the DS3904 MSB to LSB. The address
byte consists of 101000 binary followed by A0 then the
R/
W bit. If the R/W bit is high, a read operation is initiat-
ed. If the R/W bit is low, a write operation is initiated.
For a device to become active, the value of the A0 bit
must be the same as the hard-wired address pins on
the DS3904. Upon a match of written and hard-wired
addresses, the DS3904 outputs a zero for one clock
cycle as an acknowledge. If the address does not
match, the DS3904 returns to a low-power mode.
Write Operations
After receiving a matching device address byte with the
R/W bit set low, the device goes into the write mode of
operation. The master must transmit an 8-bit EEPROM
memory address to the device to define the address
where the data is to be written. After the byte has been
received, the DS3904 transmits a zero for one clock
cycle to acknowledge that the memory address has
been received. The master must then transmit an 8-bit
data word to be written into this memory address. The
DS3904 again transmits a zero for one clock cycle to
acknowledge the receipt of the data byte. At this point,
the master must terminate the write operation with a stop
condition. The DS3904 then enters an internally timed
write process t
w to the EEPROM memory. All inputs are
disabled during this write cycle.
Acknowledge Polling
Once the internally timed write has started and the
DS3904 inputs are disabled, acknowledge polling can
be initiated. The process involves transmitting a start
condition followed by the device address. The R/W bit
signifies the type of operation that is desired. The read
or write sequence is only allowed to proceed if the
internal write cycle has completed and the DS3904
responds with a zero.
Read Operations
After receiving a matching address byte with the R/W
bit set high, the device goes into the read mode of
operation. A read requires a dummy byte write
sequence to load in the register address. Once the
device address and data address bytes are clocked in
by the master, and acknowledged by the DS3904, the
master must generate another start condition (repeated
start). The master now initiates a read by sending the
device address with the R/W bit set high. The DS3904
acknowledges the device address and serially clocks
out the data byte. The master responds with a NACK
and generates a stop condition afterwards.
See Figures 4 and 5 for command and data byte struc-
tures as well as read and write examples.
2-Wire Serial Port Operation
The 2-wire serial port interface supports a bidirectional
data transmission protocol with device addressing. A
device that sends data on the bus is defined as a trans-
mitter, and a device receiving data as a receiver. The
device that controls the message is called a “master.”
The devices that are controlled by the master are
“slaves.” The bus must be controlled by a master
device that generates the SCL, controls the bus
access, and generates the start and stop conditions.
The DS3904 operates as a slave on the 2-wire bus.
Connections to the bus are made through SCL and
open-drain SDA lines. The following I/O terminals con-
trol the 2-wire serial port: SDA, SCL, and A0. Timing
diagrams for the 2-wire serial port can be found in
Figures 2 and 3. Timing information for the 2-wire serial
port is provided in the AC Electrical Characteristics
table for 2-wire serial communications.
The following bus protocol has been defined:
Data transfer can be initiated only when the bus is
not busy.
During data transfer, the data line must remain stable
whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as con-
trol signals.
Accordingly, the following bus conditions have been
defined:
Bus Not Busy: Both data and clock lines remain high.
Start Data Transfer: A change in the state of the data
line from high to low while the clock is high defines a
start condition.
Stop Data Transfer: A change in the state of the data
line from low to high while the clock line is high defines
the stop condition.