Rainbow Electronics ATmega64L - Manual (Page 99)

99
ATmega16(L)
2466B–09/01
Figure 47. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter overflow flag (TOV1) is set each time the counter reaches BOTTOM.
When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag
is set accordingly at the same timer clock cycle as the OCR1x registers are updated with
the double buffer value (at TOP). The interrupt flags can be used to generate an inter-
rupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is
higher or equal to the value of all of the compare registers. If the TOP value is lower
than any of the compare registers, a compare match will never occur between the
TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are
masked to zero when any of the OCR1x registers are written. As the third period shown
in Figure 47 illustrates, changing the TOP actively while the Timer/Counter is running in
the phase correct mode can result in an unsymmetrical output. The reason for this can
be found in the time of update of the OCR1x register. Since the OCR1x update occurs at
TOP, the PWM period starts and ends at TOP. This implies that the length of the falling
slope is determined by the previous TOP value, while the length of the rising slope is
determined by the new TOP value. When these two values differ the two slopes of the
period will differ in length. The difference in length gives the unsymmetrical result on the
output.
It is recommended to use the phase and frequency correct mode instead of the phase
correct mode when changing the TOP value while the Timer/Counter is running. When
using a static TOP value there are practically no differences between the two modes of
operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on
the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM1x1:0 to 3 (See Table 44 on
page 104). The actual OC1x value will only be visible on the port pin if the data direction
for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by set-
ting (or clearing) the OC1x register at the compare match between OCR1x and TCNT1
when the counter increments, and clearing (or setting) the OC1x register at compare
match between OCR1x and TCNT1 when the counter decrements. The PWM frequency
OCRnx / TOP Update
and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)