Rainbow Electronics DS1857 - Manual (Page 20)

DS1857
Dual Temperature-Controlled Resistors with
External Temperature Input and Monitors
20 ____________________________________________________________________
2-Wire Serial Port Operation
The 2-wire serial port interface supports a bidirectional
data transmission protocol with device addressing. A
device that sends data on the bus is defined as a trans-
mitter, and a device receiving data as a receiver. The
device that controls the message is called a master.
The devices that are controlled by the master are
slaves. The bus must be controlled by a master device
that generates the serial clock (SCL), controls the bus
access, and generates the start and stop conditions.
The DS1857 operates as a slave on the 2-wire bus.
Connections to the bus are made through the open-
drain I/O lines SDA and SCL. The following I/O termi-
nals control the 2-wire serial port: SDA, SCL. Timing
diagrams for the 2-wire serial port can be found in
Figures 5 and 6. Timing information for the 2-wire serial
port is provided in the AC Electrical Characteristics
table for 2-wire serial communications.
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain high.
Start data transfer: A change in the state of the data
line from high to low while the clock is high defines a
start condition.
Stop data transfer: A change in the state of the data
line from low to high while the clock line is high defines
the stop condition.
Data valid: The state of the data line represents valid
data when, after a start condition, the data line is stable
for the duration of the high period of the clock signal. The
data on the line can be changed during the low period of
the clock signal. There is one clock pulse per bit of data.
Figures 5 and 6 detail how data transfer is accomplished
on the 2-wire bus. Depending upon the state of the R/W
bit, two types of data transfer are possible.
Each data transfer is initiated with a start condition and
terminated with a stop condition. The number of data
bytes transferred between start and stop conditions is
not limited and is determined by the master device. The
information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Within the bus specifications a regular mode (100kHz
clock rate) and a fast mode (400kHz clock rate) are
defined. The DS1857 works in both modes.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the byte has been received. The master device
must generate an extra clock pulse which is associated
with this acknowledge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is a stable low during the high period
of the acknowledge related clock pulse. Setup and
hold times must be taken into account. A master must
signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked
out of the slave. In this case, the slave must leave the
data line high to enable the master to generate the stop
condition.
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the command/control byte. Next follows a number
of data bytes. The slave returns an acknowledge
bit after each received byte.
2) Data transfer from a slave transmitter to a master
receiver. The master transmits the first byte (the
command/control byte) to the slave. The slave
then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to
the master. The master returns an acknowledge
bit after all received bytes other than the last byte.
At the end of the last received byte, a not
acknowledge can be returned.
The master device generates all serial clock pulses and
the start and stop conditions. A transfer is ended with a
stop condition or with a repeated start condition. Since
a repeated start condition is also the beginning of the
next serial transfer, the bus will not be released.
The DS1857 can operate in the following three modes:
1) Slave Receiver Mode: Serial data and clock are
received through SDA and SCL, respectively.
After each byte is received, an acknowledge bit is
transmitted. Start and stop conditions are recog-
nized as the beginning and end of a serial trans-
fer. Address recognition is performed by hardware
after the slave (device) address and direction bit
have been received.
2) Slave Transmitter Mode: The first byte is
received and handled as in the slave receiver
mode. However, in this mode the direction bit indi-
cates that the transfer direction is reversed. Serial