Rainbow Electronics BR24L64FJ-W User Manual
Page 10
BR24L64-W / BR24L64F-W / BE24L64FJ-W
Memory ICs
10/25
zByte write
SDA
LINE
WP
S
T
A
R
T
SLAVE
ADDRESS
1 0
0
1
R
/
W
W
R
I
T
E
A
C
K
A
C
K
D7
DATA
D0
S
T
O
P
Fig.8 BYTE WRITE CYCLE TIMING
A
C
K
1st WORD
ADDRESS
2nd WORD
ADDRESS
A
C
K
WA
0
WA
12
∗
Don't care
∗ ∗ ∗
A0
A1
A2
•
By using this command, the data is programmed into the indicated word address.
•
When the master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory
array.
zPage write
Fig.9 PAGE WRITE CYCLE TIMING
SDA
LINE
WP
S
T
A
R
T
SLAVE
ADDRESS
1 0
0
1
R
/
W
W
R
I
T
E
A
C
K
A
C
K
A
C
K
D7
DATA (n)
D0
DATA (n+31)
D0
S
T
O
P
A
C
K
1st WORD
ADDRESS (n)
2nd WORD
ADDRESS (n)
A
C
K
WA
0
WA
12
∗
Don't care
∗ ∗ ∗
A0
A1
A2
•
This device is capable of thirty-two byte page write operation.
•
When two or more byte data are inputted, the five low order address bits are internally incremented by one after the
receipt of each word. The eight higher order bits of the address (WA12 to WA5) remain constant.
•
If the master transmits more than thirty-two words, prior to generating the STOP condition, the address counter will
“roll over”, and the previous transmitted data will be overwritten.